ESPERIMENTO MPGD_NEXT CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

INTRODUZIONE Nostra precedente audizione in CSN V: 29/9/2015 – allora: “proposta di esperimento” Oggi presentiamo il nostro lavoro dei primi 15 mesi Fase iniziale del secondo anno di finaziamento Questa audizione e’ stata preceduta da un meeting approfondito con i nostri referee il giorno 23/3/2017 OUTLOOK MPGD_NEXT, richiamo dei dati essenziali Un sommario dell’attivita’ svolta Collaborazioni e sinergie Aspetti finanziari CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

THE CONTEXT MicroPattern Gas Detectors (MPGD) are ideal tools for fundamental research contributing to the excellence in science (f. i. : present and future large scale use in LHC experiments) applications beyond science (better society) In spite of the extremely relevant recent progress in the field, still a long way to go towards: the ultimate limits of MPGD performance simplified construction technologies to favour very large scale applications in HEP technology dissemination beyond HEP in this context, in INFN : Expertise in MPGDs (related to exp.s: ATLAS, CMS, COMPASS, LHCb, KLOE2, TOTEM, Jlab-HallA, …) dedicated infrastructures (constructions for the exp.s) EXTERNAL FOUNDS (AIDA-2020) essential manpower for 3 participants CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MPGD-NEXT, PROJECT 3-year project 2016-2018 5 INFN UNITS: BA, LNF, NA, RM3, TS 6 TASKS (all related to hot items in the world-wide MPGD panorama) DEVELOPMENT OF NOVEL ARCHITECTURES (4 tasks) INSTRUMENTAL DEVELOPMENTS (2 tasks) DEVELOPMENT OF NOVEL MPGD ARCHITECTURES INSTRUMENTAL DEVELOPMENTS CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

TASK BY TASK CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

THE RESISTIVE-WELL DETECTOR IL PROGRAMMA PER IL 2016 è STATO COMPLETATO CON SUCCESSO: STUDI DIPENDENZA DELLE PERFORMANCE DEL DETECTOR DAL PIANO RESISTIVO CON PROTOTIPI SINGLE –RESISTIVE-LAYER (LOW RATE APPLICATIONS - PUBBLICAZIONE PRONTA PER ESSERE SOTTOMESSA). TEST DI DEPOSIZIONE PER SPUTTERING DI DLC EFFETTUATI CON SUCCESSO PRESSO «Be-sputter» IN GIAPPONE (A.OCHI) ANCHE SE SI VORREBBE CERCARE UNA SOLUZIONE EUROPEA SE NON ITALIANA (CONTATTI IN CORSO – vedi richiesta supporto) REALIZZAZIONE DELLA VERSIONE DEL RIVELATORE AD ALTA RATE, BASATA SU SCHEMA A DOPPIO LAYER RESISTIVO CON «CONDUCTIVE VIAS» DI CONNESSIONE TRA I DUE LAYERS: PROTOTIPI REALIZZATI CON READOUT A STRIP (400 um STRIP-PITCH), TEST CARATTERIZZAZIONE IN LAB COMPLETATI (pubblicazione in preparazione  milestone – 100%) TEST BEAM - FINE 2016 PER MISURE DI RISOLUZIONE TEMPORALE (FINANZIATO PARZIALMENTE DA COMMISSIONE-5 TRAMITE LO SBLOCCO DEI FONDI SJ DI MISSIONE di 4 K€ ): pubblicazione in preparazione Compact: single amplification stage Thanks to the resistive plane: very realable almost completely discharge-free adequate for high particle rates O(1MHz/cm2) thanks to the segmented-resistive-layer Expected performance: gain ≥104 rate capability ∼1 MHz/cm2 space resolution <60 µm. CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

THE RESISTIVE-WELL DETECTOR 5.7 ns dominated by FEE CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

Multi μ-drift gaps in fully resistive MPGD Fully resistive structures to allow fully electrical transparency of the generated signals (R-WELL and/or micromegas-like structure with MESH in polyimide) O(100 ps): adding up the fast signals of the multi μgap (as in MRPC) preserving high rate capability Applications Tracking and triggering in HEP experiments (fast timing applications) particle flow calorimetry imaging In collaboration with a CERN group Part of the European Patent THRAC: EP 14200153.6 “Accordo per la protezione e lo sfruttamento della proprietà intellettuale tra INFN e CERN” approvato CD 29/3/2015 CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

Multi μ-drift gaps in fully resistive MPGD The first result, V1 2 layers s_t ~ 2 ns A technical issue with the available Flexible Copper-Clad Laminate (FCCL): Single-mask etching needed for well structures Single-mask – too large hole diameter when using 125 um FCCL (with 50 um OK) In the meanwhile, V3 4 layers Transparency proven CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

High performance MICROMEGAS Goal: improved Resistive MicroMegas (MM) with small pad read-out for high rate capability till ~1 MHz/cm2  Small Pads Resistive MM Applications: Large area fine tracking and trigger (one possible application: ATLAS very forward extension of the muon tracking) Sampling Hadron Calorimetry Small Pads Resistive Micromegas: Small Pad pattern with EMBEDDED resistors, inspired by a similar R&D by COMPASS (pixelized MM). We aim at reducing the pad size from ~1cm2 to <3mm2 The construction technique depends on the pad-size Larger-size prototypes with embedded electronics in 2017 CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

High performance MICROMEGAS PADDY2 results 100% 98% cluster 3 s tracking CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

High-gain hybrid MPGD MICROMEGAS The High–gain hybrid MPGD THGEM discharges propagate through the m-mesh only when the HV is critical (>700 V; operative conditions <600 V) negligible effect of a discharge on nearby pads THGEM Anomalous discharge rates related to local defects Paschen test: a crucial tool for quality control and quality improvements phenomenological curve: Max V before breakdown function of Gas, P, electrode distance The High–gain hybrid MPGD From the state-of-the-art of THGEM, MM high gain O(106)  cover large areas at moderate costs effectively detect intrinsically feeble signals (single photons) Variety of handles to reach the goal: Resistive MM multiple THGEM layers novel THGEM substrate material optimised THGEM and MM segmentation HV supply schemes So far: Discharge studies (completed) THGEMs by novel substrate material  PERMAGLAS (completed) Next step: Improved resistive MM Discharging pad Next pad, gain reduction ~ 4% only -700 V CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

High-gain hybrid MPGD THGEMs by PERMAGLAS THGEM by PERMAGLAS fully validated, superior to FR4 CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MPGD dedicated FE Electronics Goal: a new very dense Front-End electronics characterized by a low-power consumption, with very low-noise, selectable-gain complying high rate and harsh radiation environments for high timing performance HEP applications with large area MPGDs. ASIC requirements: For detectors with space resolution ~ 100 μm time resolution of the order of a few hundreds of ps good transparency to the radiation minimization of the inefficiencies due to the pile-up effects Large covered area  electrode parasitic capacitances involved will be of the order of 50-100 pF Rate capability 50-100 kHz either a separate chain or a dedicated signal processing chain for position and timing measurements an adequate digital pipeline length to account for trigger latency (2) ASIC technology: both consumer and communication industries push toward smaller, more efficient and more integrated devices a new chip development based on the state-of-art of the process technology is not always the best choice both because of the high costs involved in the ASIC prototyping also using MPW (Multi Project Wafer Runs) runs and of the smaller upper and lower voltage boundaries of the voltage swing of the sensitive nodes unavoidable in deep submicron technologies design kits for older technologies have already been fully qualified resulting in more reliable simulations of the design.  At the moment, the best possible compromise can be found in using the 130 nm process technology. (3) Project Time Development: a) The 2016 activity: the design of a few analog blocks necessary to define the ASIC architecture including its electrical simulation and thereafter b) the design of the related layout as well as the post layout simulation. c) Will be developed the FADC block design and the fast discriminator too; selectable gain for large charge interval values (0.160 fC) and large input capacitance 8-bit FADC : 2 stages d) After that will be individuated the better TDC architecture fulfilling the requirements imposed by the particular application. e) Very crucial will be the choice of the Technology for this peculiar application CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MPGD dedicated FE Electronics Example of design simulations: TDC NEXT STEPS: Test and verification of the ASIC Test of the ASIC with FTM 2nd version design: adjusting first version & charge measurement circuit design CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MPGD-dedicated HV system Main goal: match the HV PS MPGD-requirements not commercially available true real-time monitoring of the main parameters (voltage, current) the fast control of the HV channels the use of local intelligence for the application of feedback protocols when pre-breakdown conditions are detected HV generated at the detector level: HV cabling, connectors, space constrains, cost, accumulated charge issues Modularity of the system: large size projects employing MPGDs may use a large number of channels (M/S architecture) Compactness Goal parameters: Time stamp resolution for current and voltage monitoring in the order of 10 ns or better High resolution voltage monitoring better than 0.5 Volt on several kVolt scale at sampling rate > 100 kHz Precise current monitoring at the level of 10 pA at sampling rate > 100 kHz CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MPGD-dedicated HV system Activity grouped in 3 items completed/ongoing Selection of the DC to DC converter (Commercial device) by ripple measurements and response linearity 2. ADC Board FMC standard adopted, the custom-made Pico ammeter (Custom made) ADC selected: 8-Bit 500 MSPS A/D Converter ADC08500 ADC board: custom design, built and successfully tested ADC self-calibration, multiple ADC synchronization capability Low-Pin-Count FMC connector 3. Carrier (Commercial) Zed Board based on hybrid Xilinx Zynq commercial carrier including high throughput low-pin-count FMC Fully Programmable System-on-Chip (SoC) device combining a ‘hard’ dual core ARM processor (Cortex-A9) with an FPGA fabric (FPGA Artix-7 or Kintex-7) Programming on going, ADC already read at 500 MSPS ISEG BP040105n12 Fourier transf. Ripple < 2 mV pp CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MILESTONES 2016 (*) (*) work completed, paper is being written, not yet submitted CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MILESTONES 2017 CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MPGD-NEXT, SYNERGIES RD51 : networking mondiale sui MPGD I gruppi in MPGD-NEXT sono membri RD51 Per l’INFN RD51 e’ nato in CSN I e il networking continua ad essere seguito dalla CSN I (con l’eccezione di 2 gruppi) Referaggio Oneri finanziari (modesti) del networking 10 gruppi, per il 2015: 32 keuro per collaboration fee e meeting collaborazione AIDA2020 – progetto RIA (Research & Innovation Actions) finanziato da UE Alcuni proponenti MPGD-NEXT sono membri AIDA2020 WP13: Innovative Gas Detectors In totale 134 keuro su 4 anni : MANPOWER Tale personale sara’ impiegato per lavorare su MPGD-NEXT Va rendicontato AIDA2020 (redicontazione imposta da UE) CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MPGD-NEXT, SYNERGIES SINERGIE CON ALTRI ESPERIMENTI INFN Task 1,2, 5 con CMS (finanziamento large size e ingegnerizzazione) Task 1, 5 con LHCb, RD_FA (finanziamento RD_FA per studi ingegnerizzazione high rate) Task 2 con RD_FA Task 4, 6 con COMPASS (background culturale e di infrastrutture locali) Task 4, 6 con RD_FA (gli sviluppi in MPGD_NEXT potranno in parte essere travasi nei progetti per la sperimentazione a EIC) Task 3 con ATLAS Task 2, 5 con MPGD_FATIMA  Largo spettro di impatto su attivita’ di ricerca dell’Istituto CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre

MPGD-NEXT, financial matter Si chiede lo sblocco del s.j. missioni (5 k€) “Il SJ e' per i vari Test Beam, condizionato alla presentazione del calendario approvato dei test.» Task 1, uR-WELL: PSI 19/6-2/7/2017 Task 2, FTM: CERN, H4, 7-19/7/2017 (RD51 common test beam) Task 3, High performance MICROMEGAS: CERN, H4, Si restituisce il s.j. Consumi LNF (6 k€) Per difficolta’ tecniche nella fotolitografia del kapton di spessore 125 um (stand-by) Nuova richiesta: Consumi LNF (10 k€) R&D con industria italiana per sputtering LDC per layer resistive in MPGD Strategico, anche per molti altri MPGDs Nuova esigenza, maturate nel corso dell’attivita’ Cifra commensurata al costo, come da contatti preliminari con la ditta (LAFER, Piacenza) Si sottolinera il forte disagio della collaborazione nel portare avanti il programma previsto con un budget annuale di missioni di 11 k€ per 5 sedi, 6 task e 28 fisici (6.5 FTE + 0.5 da AIDA-2020) [dati 2017] CSN V, 3-5/4/2017 MPGD-NEXT Silvia Dalla Torre