SOTTOSISTEMA DI MEMORIA M. Mezzalama - M. Rebaudengo Politecnico di Torino Dip. di Automatica e Informatica

Le problematiche Velocità del host bus vs velocità memoria DRAM: Soluzioni tecnologiche (fast operative mode dram) Soluzioni architetturali (interleaving) Refresh Rilevazione-correzzione errori Prestazioni del dram controller e chip set

ABUS N bit M bit Banco 1 Sel di Banco & control CS Segnali di stato e timing DBUS Banco n CS READY

DRAM 1Mb (256 x 4) Bus degli indirizzi multiplato dai segnali di RAS e CAS (M/2 bit)

Cicli DRAM Ciclo READ Ciclo WRITE (2 tipi) Ciclo REFRESH Ciclo FAST OPERATIVE

Ciclo base DRAM Tacc = 70 ns =Tras Tcycle = 2 * Tacc

CICLI REFRESH

FAST OPERATIVE Si basano sulla possibilità tecnologica di selezionare celle adiacenti della matrice senza dover completare un ciclo completo di RAS. Sostanzialmente leggono tutte le celle associate ad una riga Vengono adoperate quando si debbano fare trasferimenti di dati con indirizzi adiacenti, come nel caso dei cicli burst per aggiornare la cache. In tal caso si leggono tanti byte adiacenti quanti contenuti in una line di cache Esistono tre tipi di Fast operative mode: Asincrono Sincrono Protocol based

La famiglia delle DRAM EDO RAM BEDO RAM Le componenti più veloci della asincrone BEDO RAM Le componenti più veloci della mia famiglia SD RAM sincrone DDR RAM Protocol based RDRAM (Rambus RAM)

DDR DRAM DDR SDRAM or double-data-rate synchronous dynamic random access memory is a type of memory integrated circuit used in computers. It achieves greater bandwidth than the preceding single-data-rate SDRAM by transferring data on both the rising and falling edges of the clock signal (double pumped). This effectively nearly doubles the transfer rate without increasing the frequency of the front side bus. Thus a 100 MHz DDR system has an effective clock rate of 200 MHz when compared to equivalent SDR SDRAM, the “SDR” being a retrospective designation. With data being transferred 8 bytes at a time DDR RAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 8 (number of bytes transferred). Thus with a bus frequency of 100 MHz, DDR-SDRAM gives a max transfer rate of 1600 MB/s.

DDR DRAM DDR-200: DDR-SDRAM memory chips specified to operate at 100 MHz DDR-266: DDR-SDRAM memory chips specified to operate at 133 MHz DDR-333: DDR-SDRAM memory chips specified to operate at 166 MHz DDR-400: DDR-SDRAM memory chips specified to operate at 200 MHz DDR is being replaced by DDR2 SDRAM, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR2 will be Rambus XDR-DRAM. It is expected that DDR2 will become the standard, since QDR (Quad Data Rate) is too complex to implement, while XDR is lacking support. The difference of DDR2 to DDR is a doubled bus frequency for the same physical clock rate, thus doubling the effective data rate another time

DDR2 DRAM Chips DDR2-400: DDR-SDRAM memory chips specified to run at 100 MHz, I/O clock at 200 MHz DDR2-533: DDR-SDRAM memory chips specified to run at 133 MHz, I/O clock at 266 MHz DDR2-667: DDR-SDRAM memory chips specified to run at 166 MHz, I/O clock at 333 MHz DDR2-800: DDR-SDRAM memory chips specified to run at 200 MHz, I/O clock at 400 MHz Sticks/Modules PC2-3200: DDR2-SDRAM memory stick specified to run at 200 MHz using DDR2-400 chips, 3.200 GB/s bandwidth PC2-4200: DDR2-SDRAM memory stick specified to run at 266 MHz using DDR2-533 chips, 4.267 GB/s bandwidth PC2-5300: DDR2-SDRAM memory stick specified to run at 333 MHz using DDR2-667 chips, 5.333 GB/s bandwidth1 PC2-6400: DDR2-SDRAM memory stick specified to run at 400 MHz using DDR2-800 chips, 6.400 GB/s bandwidth Note: DDR2-xxx (or DDR-xxx) denotes effective clockspeed, whereas PC2-xxxx (or PC-xxxx) denotes theoretical bandwidth (though it is often rounded up or down). Bandwidth is calculated by taking effective clockspeed and multiplying by eight. This is because DDR2 can transfer 64 bits of data each clock cycle, and since a byte is comprised of 8 bits, this equates to 8 bytes of data per clock cycle.

DRAM Controller M/2 ABUS MPX M/2 ABUS M/2 ABUS REFRESH RD/WR RASi CASi TIMING & CONTROL RASi CASi CPU cycle WE DATA control - DBUS READY