Progetto di circuiti su FPGA

Flusso di Sviluppo Descrizione comportamentale Simulazione comportamentale Sintesi Descrizione strutturale (Netlist) Simulazione con ritardi approssimativi Implementazione Simulazione dettagliata Download Simulazione sul campo

Descrizione Comportamentale Descrizione del tutto ideale del funzionamento del dispositivo ad alto livello di astrazione non prevede ritardi di alcun tipo Es: C <= (A + B)* C

Sintesi Traduzione dalla descrizione comportamentale all strutturale, ossia a livello di porte logiche (Netlist) Si basa sulla presenza di opportune librerie E’ suddivisa nelle seguenti fasi Analisi (analisi sintattica del sorgente) Compilazione traduzione a livello RTL (Register Transfer Level) estrazione delle macro Ottimizzazione (miglioramento della logica, espansione delle macro) E’ un procedimento “guidato” abbisogna di opportuni vincoli Lib. Vincoli

Descrizione Strutturale Descrizione del circuito il termini di blocchi logici (porte, flip-flop, registri, memorie, …) presenti in libreria opportunamente collegati ossia in termini di NETLIST Le informazioni portate da questa descrizione sono: Ritardi della logica (ma non dei collegamenti) Area occupata dalla logica (ma non dai collegamenti) Z C D A B

Implementazione Traduce la descrizione a celle logiche in una opportuna descrizione fisica maschere per il layout (ASIC) file di download (FPGA - CPLD) Si divide in quattro fasi Translate ( fusione con blocchi pre-configurati) Mapping (mappatura della logica nei CLB) solo per FPGA Placement (Posizionamento dei blocchi logici) Routing Collegamento tra CLB Il procedimento si basa su vincoli implementativi

Descrizione Dettagliata La descrizione del circuito e’ molto vicina a quelle che saranno le reali prestazioni. Vi sono infatti informazioni su Ritardi della logica Ritardi nei collegamenti Area occupata dalla logica Area occupata dai canali di collegamento Dettaglio sull’ ubicazione di ogni singola porta logica e/o dei piedini di I/O

Back Annotation Alcuni dei risultati ottenuti ai vari passi del procedimento spesso vengono utilizzati in un procedimento di “back-annotation” ossia vengono riportati ai passi superiori quali vincoli o per avere descrizioni piu’ dettagliate del funzionamento del circuito anche ad alti livelli di astrazione Vincoli Ritardi

ISE Software Flow FPGA Design Workshop

Software makes a difference Device capabilities are worthless if you can’t use them in YOUR course Design software should support all ranges of designs from CPLD to the high-density FPGA Works with YOUR design flow minimize impacts to the design cycle work with the tools you already own

Foundation Series ISE Foundation Series ISE (Integrated Software Environment) For PC platforms: Win98, Win2000, and NT4.0 For UNIX platforms: HP and Solaris

Xilinx Design Flow Implement Plan & Budget Create Code/ Schematic HDL RTL Simulation Implement Functional Simulation Synthesize to create netlist Translate Map Place & Route Attain Timing Closure Timing Simulation Create Bit File

Advanced design management through project navigator Unix & PC platforms Complete file management Automates design flow Entry Synthesis Implementation Simulation Programming

Device Support New leading-edge device families ISE advantages can be leveraged across all device families and design sizes

Processes and Tools Step 1:Design Step 2: Synthesize to create netlist Step 3: Implement design Some tools are listed multiple times with different task names Step 4: Configuration

Context Sensitive Flow Only relevant processes are displayed to the user Guides the user to the “next step” for that source HDL Module Selected Process Available Includes Synthesis and P&R Only HDL Simulation process is available HDL Test Bench Selected

ISE Push Button Flow Select a desired end result -- all necessary processe and dependencies automatically run to produce the result Simple three-step process to get results 1 2 3 Double Click Desired End Point Add Files Select Top Level

Lab 1: ISE Flows Introduction to the ISE flow Step through the FPGA design flow with a simple design Download the generated bitstream to the XESS - XSA50 demo board

. . . Design Entry Two design entry methods: HDL or schematic Architecture Wizard and Core Generator available to assist design entry Whichever method you use, you will need a tool to generate an EDIF netlist to program a Xilinx FPGA Popular synthesis tools: Synplify, Leonardo Spectrum, FPGA Compiler II, and XST Simulate design so that it works as expected! Plan & Budget Create Code/ Schematic HDL RTL Simulation . . . Functional Simulation Synthesize to create netlist

Schematic Source File Create a new schematic source: Project  New Source  Schematic Components from Xilinx Unified Libraries HDL keywords cannot be used on schematics Unified components require all input pins to be connected Tie unused pins, both inputs and outputs, to GND or VCC

Options and Symbols The Options tab selections change, depending on which function is selected For example, if you are adding a net name, the net name options would be shown Components are divided into categories Exact symbols are located in the Symbol box Symbol Name Filter for easier search Orientation Rotate 0, 90,180, 270 Mirror and rotate 0, 90, 180, 270

HDL Source File Types of HDL source files VHDL logic description (.vhd extension) Verilog logic description (.v extension) ABEL-HDL logic description (.abl extension) Selecting these source types will open a text editor for you to enter the design code

Xilinx CORE Generator System GUI Cores can be organized by function, vendor, or device family Core type, version, device support, and vendor

Core Customize Window Core Overview tab provides version information and a brief functional description Contact tab provides information about the vendor Parameters tab allows you to customize the core Data sheet access

Lab 2: ECS - Simulation - Synthesis Introduction to ECS Step through the process of creating a schematic design Generate a hierarchical schematic Simulation (on different abstraction levels) Synthesis (and optimization)

5.1i Synthesis Solutions ISE provides integrated interfaces to: Mentor Leonardo Spectrum Synplicity Synplify/Pro Both with cross-probing and synthesis launching FPGA Compiler II supported through Alliance flow ISE Foundation includes basic synthesis with Xilinx Synthesis Technology (XST)

XST Flow ISE 5.1i VHDL Verilog Supported Families: Virtex XC9500 PC & WS Supported Families: Virtex XC9500 Virtex-E XC9500XL Virtex-II XC9500XV Virtex-IIPro CoolRunner Spartan-II CoolRunner-II Spartan-IIE Constraints Synthesis Technology Specific Optimization To Implementation Tools Synthesis Report File .NGC .LOG

Xilinx Implementation Once you generate a netlist, you can implement the design There are several outputs of implementation Reports Timing simulation netlists Floorplan files FPGA Editor files and more! Implement . . . Translate Map Place & Route .

What is Implementation? More than just “Place & Route” Implementation includes many phases Translate: Merge multiple design files into a single netlist Map: Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) Place & Route: Place components onto the chip, connect them, and extract timing data into reports Each phase generates files that allow you to use other Xilinx tools (such as Floorplanner, FPGA Editor, XPower, Multi-Pass Place & Route)

Implement Each implementation stage can be expanded to view the available sub-tools and sub-processes Translate Create post-translate simulation model Map Floorplan Manual route with FPGA Editor Place & Route Static timing Floorplanner, view placed design FPGA Editor, view routed design Analyze power

Download Once a design is implemented, you must create a file that the FPGA can understand This file is called a bit stream: a BIT file (.bit extension) The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

Program the FPGA There are two ways to program an FPGA Through a PROM device You will need to generate a file that the PROM programmer will understand Directly from the computer Use the iMPACT configuration tool

RTL Viewer for XST Helps debug design connectivity, design speed

Architecture Wizards Simplifies design of complex components Supports: Generates HDL files & .ucf Supports: DCM RocketIOTM transceivers Including Channel Bonding

State Diagram Source Files with .dia extension Selecting this source type will invoke StateCAD

HDL Bencher Multiple Clock and Asynchronous Signal Support 2) Choose Clocks 3) Associate Signals with Clocks or Assign as Asynchronous 1) Select Multiple Clocks and/or Asynch Signal Support

HDL Bencher Multiple Clock and Asynchronous Signal Support 4) Specify Timing for Each Clock 5) Define Waveforms

Incremental Design Make small changes quickly! Re-implements only the changed modules Keeps placement and routing Easy set-up through floorplanning along HDL hierarchy boundaries Works with HDL designs don’t optimize across hierarchy More turns per day More repeatable results

PACE simplifies pin and area assignments PACE (Pinout and Area Constraints Editor) Create groups for busses and standard outputs Color-coded banks Drag-and-drop pin assignments Interactive DRC Automatic differential I/O pairing Logic size to area checking

Constraints Improvement Wizard Gives suggestions on how to constrain unconstrained paths

Summary The Xilinx design process contains only four steps: design, synthesize, implement, configure The Xilinx design process can all be done through the ISE Project Navigator