ESTREMO ERC (Europen Research Council) Starting Grant Research proposal Partecipanti 1.ARCES ( Advanced Research Center on Electronic Systems ), Facoltà di Ingegneria, Università di Bologna 2.CNR-IMM - Bologna 3.Texas Instruments, Inc., Dallas, Texas, USA Enhancement of conductance in integrated power devices by means of strain effect and modulation techniques

ESTREMO Comè nato il consorzio –collaborazione fra ARCES e T.I. USA già esistente sullo studio di dispositivi per applicazioni Smart Power –limitazioni nella conduzione dei transistor DMOS »… velocity saturation effects in the drift region limit the device conductance, leading to a detrimental reduction of the maximum current drive at high voltages and to a premature current saturation… –Nel progetto si indagheranno due aspetti strain engineering conductance modulation

ESTREMO Comparison of the turn-on characteristic of the reference rugged LDMOS with that of a strained one. A 5-MPa tensile stress along the transport direction is applied under the STI region.

ESTREMO Coinvolgimento IMM –Misure di deformazione reticolare in silicio CBED LACBED NBD (Nano Beam Diffraction) –Misure in strutture grandi condizioni più rilassate per la misura possibilità di ottenere geometrie ad hoc da T.I. –strain uniassiali –possibilità di sviluppo misure in campi di strain rapidamente variabile È stata esplicitamente richiesta da ARCES la possibilità di inserire nel progetto una parte di sviluppo metodologico della misura di strain

ESTREMO CBED LACBED NBD

ESTREMO – descrizione del lavoro WPTitleWP Leader WP1New concepts for strain engineering and conductance modulationARCES WP2Device characterization and strain measurementsARCES/IMM WP3Test pattern fabricationTI

ESTREMO – WP1 Task TitleMonths T1.1 Acquisition of simulation tools for process-induced strain engineering. M1-M3 T1.2 Investigation on locally strained devices with different crystal orientation and geometrical parameters. M4-M36 T1.3 Investigation on different conductance modulation approaches. M4-M36 T1.4 Development of new models for the reliability analysis in LDMOS. M4-M36 T1.5 Physical design of test structures and devices to be realized in test chip #1 M4-M8 T1.6 Physical design of best devices based on new concepts to be realized in test chip #2 M14-M18 T1.7 Physical design of best devices based on new concepts to be realized in test chip #3 M24-M28

ESTREMO – WP2-WP3 Task TitleMonths T2.1 Electrical characterization of devices fabricated in test chip #1. M12-M14 T2.2 Microstructure analysis of test modules #1 M12-M16 T2.3 Electrical characterization of devices fabricated in test chip #2. M22-M24 T2.4 Microstructure analysis of test modules #2 M22-M26 T2.5 Electrical characterization of devices fabricated in test chip #3. M32-M34 T2.6 Microstructure analysis of test modules #3 M32-M36 T2.7 Development of TEM/CBED measurements of non uniform strain fields. M13-M36 Task TitleMonths T3.1 Technology setup and layout design of test chip #1. M4-M8 T3.2 Fabrication of test chip #1. M8-M12 T3.3 Technology setup and layout design of test chip #2. M14-M18 T3.4 Fabrication of test chip #2. M18-M22 T3.5 Technology setup and layout design of test chip #3. M24-M28 T3.6 Fabrication of test chip #3. M28-M32

ESTREMO – Gantt chart e m/m WP no.Y1Y2Y3 Total (P1) Y1Y2Y3 Total (P2) Y1Y2Y3 Total (P3) Total (per WP) ARCES IMM-CNRTI WP WP WP Total

ESTREMO - costs Cost Category Year 1 [1] [1] Year 2 2 Year 3 2 Total (Y1-3) 2 Total Costs of project: (by year and total) [1] [1] Adapt to actual project duration. Cost categoryYear 1Year 2Year 3Total Research staff Short-term staff Technical staff Total personnel Travel Total other costs Total direct costs Indirect costs Total costs