CHIPIX65 Status Report – July 2014 Sviluppo di un pixel chip innovativo in tecnologia CMOS 65nm per altissimi flussi di particelle e radiazione agli esperimenti.

Presentazione sul tema: "CHIPIX65 Status Report – July 2014 Sviluppo di un pixel chip innovativo in tecnologia CMOS 65nm per altissimi flussi di particelle e radiazione agli esperimenti."— Transcript della presentazione:

1 CHIPIX65 Status Report – July 2014 Sviluppo di un pixel chip innovativo in tecnologia CMOS 65nm per altissimi flussi di particelle e radiazione agli esperimenti di HL_LHC e futuri collider di nuova generazione CALL 2013 CSN5 – Responsabile Nazionale: L.Demaria L. Demaria - CHIPIX651

2 Challenges for CHIPIX65 1. Design of innovative electronics in strategic area of INFN, using the “novel” CMOS 65nm technology, with a large participation of INFN community 2.INFN is one of founding members of RD53, an international collaboration for the R&D phase of an innovative chip for the pixel detector of ATLAS and CMS at HL_LHC, and the goals of RD53 are the main focus of CHIPIX65 milestones: 1.Small pixels: 50x50um 2 (or 25x100um 2 ) 2.Large chips:>2cm x 2cm ( ~1 billion transistors) 3.Hit rates:~2 GHz/cm 2 4.Radiation:1Grad, 10 16 neu/cm 2 (unprecedented) 5.Trigger: 1MHz, 10us (~100x buffering and readout) 6.Low power - Low mass systems L. Demaria - CHIPIX65 2

3 Project breakdown (2014) N. Demaria - CHIPIX65 3 Work Packages: 1.Radiation Hardness – P.Giubilato (Pd) 2.Digital Electronics – R.Beccherle (Pi) 3.Analog Electronics - A.Rivetti (To) 4.Chip Integration - V.Re (Pv), V.Liberali (Mi) 5.Project Management – N.Demaria (To)

4 Composizione CHIPIX65 L. Demaria - CHIPIX65 4 1 PhD student more (IC-designer analog) 1 staff IC-designer digital Less for Irrad (also in ScalTech28) + IC-designer from DEI Same IC-designers + 2 additions

5 Main work done: First 180 days  Irradiation of basic test structures (Pd)  Design of Very Front End analog electronics (Pv,To)  Work on IP-block  Defining responsibility of IP-block (Ba,Mi,Pd,Pv,Pi,To)  First design of IP-block (Ba,Mi,Pv,Pi)  Digital architecture  Undergoing development of the simulation and verification framework (Pg) DESIGN activities were assuming TSMC/IMEC/CERN contract ready on spring 2014. NDA arrived only 1 week ago to all sites  impact on schedule NB: prediction of last year were for October-November 2013 (!) All this will be better shown along this presentation L. Demaria - CHIPIX65 5

6 RD53: the international context for CHIPIX65  ~ 100 members, 19 Institutes ( 2 new institutes have joined )  Bari, Bergamo-Pavia, Bonn, CERN, CPPM, Fermilab, LBNL, LPNHE Paris, Milano, NIKHEF, New Mexico, Padova, Perugia, Pisa, Prague IP/FNSPE-CTU, PSI, RAL, Torino, UC Santa Cruz.  2 institutes requesting to join: LAL/OMEGA, Sevilla  Spokes persons : Maurice Garcia-Sciveres, LBNL (ATLAS), Jorgen Christiansen, CERN (CMS) [2 year terms]  Collaboration Board (CB chair: LD)   Regular CB meetings  MOU document APPROVED  Management board : Spokes persons, CB chair, WG conveners  Monthly meetings  V.Re WG-conver Analogica   R.Beccherle newly appointed as IO-WG convener   Technical Working Groups have started  WG conveners  Regular WG meetings  First official RD53 collaboration meeting (pre-RD53 meeting in Nov. 2012)  CERN April 10-11, 64 participants: https://indico.cern.ch/event/296570https://indico.cern.ch/event/296570 L. Demaria - Report on RD53 - CMSTK week 22-07-2014 6 CHIPIX65 / INFN Ben rappresentato in RD53

7 Main 2014 CHIPIX65 contributions to RD53  Radiation WG (Padova) :  Irradiation campaign at Legnaro with low energy protons (TDD studies)  foreseen also irradiation with x-ray machine (TID)  Analog WG (Pavia, Torino)  Design of Very Front end chain, low power, low threshold (<1000e-) with synchronous and asynchronous comparators  IP-block WG (Bari, Milano, Pavia, Padova, Pisa, Torino)  16 out of 34 IP-block under INFN responsibility  Simulation WG (Perugia)  Main contributor to the development of the simulation and verification framework  Top Level WG :  Activity is at a preliminary stage. Contribution mainly from LBNL (USA)  IO WG :  Activity will start during the second half of 2014. New convener being identified now (Roberto Beccherle – Pisa) L. Demaria - CHIPIX65 7

8 RD53 WG1 (Radiation test/qualification): Summary CERN test structures (65nm nMOS & pMOS transistors) CERN: 10-keV X ray (CERN), till 200 Mrad(SiO 2 ) CPPM: 10-keV X ray (CERN), till 1Grad(SiO 2 ), 20 & 100 ºC annealing Padova: 3-MeV proton (Padova), till 1Grad(SiO 2 ), 20 & 100 ºC annealing ( 31-st March, 21-22 May 2014) TSMC test structures - FNAL layout (65 nm nMOS & pMOS transistors) Fermilab: Co-60 γ ray, -20 ºC irradiation, till 1Grad(SiO 2 ) Results from Padova L. Demaria - CHIPIX65 8

9 Digital Pixel architecture DUT: behavioral, time-based description of a simple pixel chip with basic functionality (conversion of hits into discriminator outputs, computation of hit time of arrival and amplitude, trigger selection, column arbitration). UVM verification components connected to interfaces defined in DUT: hit generation (different classes of typical detector hits can be generated) monitoring of pixel chip input and output conformity checks and statistics collection. Goal: Simulation and optimization of pixel chip architectures to be implemented in prospective next generation pixel readout chips. VEPIX53: a flexible Verification Environment for PIXel chips in RD53 in SystemVerilog + UVM (collaboration with RD53, http://rd53.web.cern.ch/RD53/ ). 9 Perugia

10 Design of Analog VFE @ Torino Baseline Solution: Single stage front end with CSA + Discriminator (synch discr.)  Low power: 5uW/pixel cell ( or below )  (FEI4~15uW/pix analog, PSI46~6.7uW analog [RH])  Low noise: 90e - for Cd~100 fF (or below)  7 sigma=560e-; threshold max 1000e-  FAST ToT: 30ke- signal max into max 250nsec  others 400ns for 10 or 30ke-  High resolution of Digital information: 8 bits (lower resolution possible)  FEI4: 4 bits to stay in 400ns (40 MHz clock)  NO-threshold trimming via DAC  Hardware solution (corrections stored in capacitors): Never done before in pixel VFE  Dimensions: max area ~25x50 um 2 L. Demaria - INFN activities of CHIPIX65 10 Layout dimensions: 26x35 um 2

11 VFE Performance (Torino) L. Demaria - CHIPIX65 Noise vs Detector Capacitance LINEARITY ot DIGITIZED ToT (here shown up to 7 bits in 250ns 11 ENC e- #ADC counts 128 50 Cdet fF Q (Ke - ) 10 90e- @100 fF for 250ns ToT 128 MHz 256 MHz 512 MHz 100 50 100 (oscill.@512 MHz)

12 L. Demaria - CHIPIX65 12 PAVIA

13 IP Block for RD53 Out of 34 IP-block identified in RD53, INFN has proposed to contribute at ~16 of them: as main organizer (11) as participant (5) In the following few slides on first prototypes ready for submission in fall 2014 (design in 65nm already present): ADC Band-Gap SLVS driver SRAM Serialiser-deserialiser others IP-blocks could be ready for end of year 13 L. Demaria - CHIPIX65

14 Bari IP-block  Progettazione di un convertitore digitale-analogico (DAC) a 10 bit per la polarizzazione dell’elettronica di front-end 1 o prototipo da sottomettere a Ottobre 2014 Collaudo agli inizi del 2015 Implementazione di eventuali modifiche e nuova sottomissione nel 2015 Sottomissione 1 o prototipo: Q1 2015 Collaudo: Q2-Q3 2015 Implementazione di eventuali modifiche e nuova sottomissione: Q3/Q4 2015  Sviluppo di soft-IP per il controllo remoto del chip, adottando tecniche di ridondanza per aumentare la resistenza ai Single Event Upset: Q4 2014 – Q1 2015  Progettazione di un convertitore analogico-digitale (ADC) a 12 bit per il monitoring dei parametri funzionali del chip

15 IP-block (Mi) DICE RAM Cell  Interest of Milano (in CHIPIX65, applying for RD53) to develop radiation hard SRAM  array of 256x256 DICE (Dual Interlocked storage Cell) RAM cells ready for submission. Size of about 1.8x3.3 um 2  Other two designs more radiation hard also ready  This could be used either in the PUC or in the EOC Schematics Layout V.1 L.Demaria: CHIPIX65 pixel FE for HL_LHC - INFN Future Detector Workshop 2014 12 March 2014 15 SEU recovery in ~20ns

16 L. Demaria - CHIPIX65 16 PAVIA

17 PLL/SER/CDR  data IO & clock management L. Demaria - CHIPIX65 17 ORGANIZATION on-going

18 IP-cores for high speed links PISA  Standard Cell based SER/DES in CMOS 65nm  Ready for the CHIPIX65 submission in fall 2014  RTL preliminary synthesis completed  SER @ 2GHz  Worst 1.4 mW  Best 1.6 mW  DES @2GHz  Worst 6.0 mW  Best 8.3 mW  Collaboration with UCSB on high speed TX & RX differential PADs  Foreseen for end of year. Needs NDA

19 Padova IP-Block L. Demaria - CHIPIX65 19 PLL VCO : specs to be better defined.

20 CHIPIX65 2014 submissions  IP-block submission (2 blocks of 2x2 mm 2 )- October 2014 :  SLVDS (Pavia)  Band-Gap (Pavia, Milano)  SRAM(Milano)  DAC (Bari)  Serialiser/deserialiser (Pi)  Analog Very Front End submission (1 block of 2x2 mm 2 ) - October 2014  Synchronous, Auto-zeroing, FAST ToT analog front end (Torino)  Asynchronous analog front end (Pavia) Analog readout: max (12x12) pixels + Matrix: (12x32) pixel (Torino,Pavia,Pisa)  In the pipeline  Next IP blocks to be ready :  ADC (Bari), TX-RX (Pisa), Digital Logic RAdHard (Milano), PLL (?)  Pixel-Matrix with complex synthetized digital logic (pixel and readout) [Torino, Pisa, Pavia, Milano] L. Demaria - CHIPIX65 20

21 October submission: IP-block L. Demaria - CHIPIX65 21 Esercizio di floorplanning che Indica che far stare tutto su di un solo IP-block, e’ difficile e presenta svantaggi. Bandgap: includere versioni CERN, CPPM per confronto DAC: Due versioni (logica minimu size e non) Includere anche disegno DAC in tensione di Praga SRAM: Milano abbisogna di piu’ spazio se possibile (256x256 invece di 128x256 celle)

22 October submission – VFE block L. Demaria - CHIPIX65 22 1) One core AREA with ANALOG testing for ASYNC design(PAVIA) 2) One core AREA with ANALOG testing of SYNC design (Torino) 3) One core AREA with simple digital readout and measurement of ToT (slow and fast ToT) 1 2 3

23  Lavoro a Pisa (F. Morsani) e Torino  Misura del ToT con un clock generato internamente al pixel  Simulazione e ottimizzazione delle celle  Layout con il DK TSMC  Realizzazione della matrice  Test bench e sviluppo del firmware  Riutilizzo e riadattamento scheda ( Pisa )  Lavoro fatto ad oggi  disegno del circuito funzionante in ToT e binary (registrazione del solo hit) mode  setup simulazione mixed-mode (Verilog-Spectre): stimoli digitali e readout in Verilog, circuito dei pixel in Spectre (analog simulator)  simulazione e debugging del singolo pixel  Layout singole celle digitali (ritardato da mancanza contratto CERN/IMAC/CERN) – aiuto di Bari e Milano CHIPIX65 Logica nel pixel per la prima sottomissione

24 Simulazione, 5 eventi singolo pixel in vari casi, si vede bene il clock del ToT e il caso di timeout nel conteggio del ToT 24 CHIPIX65 Input signal, used in the mixed-mode digital Cadence simulation

25 Milestones declared last year N. Demaria - CHIPIX65 25 First Milestone : NO problem foreseen. Second Milestone: OK October submission but Return from TSMC end of year. quick analog-test possible.

26 RD53 Outlook  2014:  Release of CERN 65nm design kit. RD53 eagerly awaiting NDA issues to be resolved.  Detailed understanding of radiation effects in 65nm  Radiation test of few alternative technologies.  Spice models of transistors after radiation/annealing  IP/FE block responsibilities defined and appearance of first FE and IP designs/prototypes  Simulation framework with realistic hit generation and auto-verification.  Alternative architectures defined and efforts to simulate and compare these defined  Common MPW submission 1 : First versions of IP blocks and analog FEs  2015:  Common MPW submission 2: Near final versions of IP blocks and FEs.  Final versions of IP blocks and FEs: Tested prototypes, documentation, simulation, etc.  IO interface of pixel chip defined in detail  Global architecture defined and extensively simulated  Common MPW submission 3: Final IPs and FEs, Initial pixel array(s)  2016:  Common engineering run: Full sized pixel array chip.  Pixel chip tests, radiation tests, beam tests,,  2017:  Separate or common ATLAS – CMS final pixel chip submissions. L. Demaria - Report on RD53 - CMSTK week 22-07-2014 26

27 RD53 IP-block schedule L. Demaria - Report on RD53 - CMSTK week 22-07-2014 27

28 RD53 MoU L. Demaria - Report on RD53 - CMSTK week 22-07-2014 28  Few countries ready to sign through FUNDING Agency:  Netherland, Italy, France, UK  Other Institutes sign with local authority  For few Institute there might be a problem  USA Laboratories – DOE will not sign any MoU right now  Feedback needed from PSI

29 RD53 Institutes L. Demaria - Report on RD53 - CMSTK week 22-07-2014 29 Groups in the process of joining: Sevilla/Santander(CMS) UCSB(CMS) LAL/Omega (ATLAS) 9 ATLAS 8 CMS 2 CMS/ATLAS

30 RD53 Common Collaboration Fund (defined in the MoU) L. Demaria - CHIPIX65 30

31 Firma MoU di RD53  Documento pronto a essere circolato dal CERN ai vari istituti tra ora ed inizio settembre  Passi necessari nell’INFN (Informazioni da Roberto Pellegrini  Comunicazione del direttore di Torino e del presidente di gruppo 5 a Roberto Pellegrini  Testo finale MoU  Interesse a partecipare da parte dell’INFN  Oneri finianziari dell’INFN e copertura in bilancio  I 2 kCHF per il Common Collaboration Fund  R.Pellegrini prepara una delibera  Approvazione della Giunta e del Direttivo  Firma del Presidente L. Demaria - CHIPIX65 31

32 Conclusioni L. Demaria - CHIPIX65 32 Primi 6 mesi molto positivi per CHIPIX65 Layout in TSMC 65nm in 5 sedi su 6. Con NDA approvato, da settembre TUTTE le sedi potranno lavorare con 65nm Ottimo stato di avanzamento in IP-block e VFE- analogica: prima sottomisisone Ottobre 2014 Contributo a RD53 importante e presenza visibile dell’INFN Per il 2015 bisogna progredire in elettronica digitale complessa e sintetizzabile e sul top-level del chip: Importante sottomettere una small pixel array concepita completamente dall’INFN

33 Altro materiale Finanze 2014 Richieste finanziarie 2015 L. Demaria - CHIPIX65 33

34 CHIPIX65 –Finance 2014 L. Demaria - CHIPIX65 34

35 CHIPIX65 – Finance 2014 Apparati  October 2014 ~ 60 ke (order under placement NOW)  20ke*2 : IP-block  20ke : VFE analog block  Another IP-block submission end of 2014 (december) or for early February (but money to be moved with 1-2 months in advance)  we want to ask the sub-judice in Autumn Consumi  Preparation of test boards for IP-blocks, for VFE-analogic readout, for VFE digital readout  Common Collaboration Fund: contribution to RD53 for consumable 14 kCHF Missioni  1 day meeting on End October/November, inviting also ScalTech28 representative  RD53 meeting at RAL (at least in part)  IC-designer meeting L. Demaria - CHIPIX65 35

36 CHIPIX65 anno 2015 L. Demaria - CHIPIX65 36

37 Composizione CHIPIX65 L. Demaria - CHIPIX65 37 1 PhD student more (IC-designer analog) 1 staff IC-designer digital Less for Irrad (also in ScalTech28) + IC-designer from DEI Same IC-designers + 2 additions

38 Attivita’ per 2015 (1)  Radiation hardness  1) Irraggiamento con i fasci di protoni da 3-MeV, con device raffreddati per studiare l'effetto della temperatura sul danneggiamento da TID (Pd), in particolare per valori prossimi a quelli previsti nei rivelatori a pixel ad HL_LHC (T=-20C)  2) Irraggiamento con 10-keV X ray (Pd)  3) Set-up test di SEU con fasci di ioni (Pd, Pg )  4) Set-up di test per SEU con laser in laboratorio (Pg)  5) Caratterizzazione statica, di segnale e di rumore di dispositivi MOS con X-ray machine o protoni per lo studio della degradazione da TID (Pv). L. Demaria - CHIPIX65 38

39  Effettuare test di SEE dei prototipi e delle versioni del chip integrato con fasci di ioni e stimolazione Laser  Il sistema Laser e’ quello sviluppato a Perugia con cui sono stati effettuati test di AMS e che e’ stato utilizzato da MAPRad per collaudare vari chip della IMEC e della CAEN microelettronica (ora Sitael) Proposta finanziamento: SEE in laboratorio con Laser

40 Il sistema laser II SEE chip mapping higher energy lower energy Comparison of Ion beam And Laser

41 Attivita’ per il 2015 (2)  IP-Block (WP2-WP3) whole 2015  1) Sviluppo di tutti i prototipi di IP-block di responsabilità INFN. Seconda iterazione degli IP-block sviluppati nel 2014, e prime (genn/febr 2015) versioni di:  PLL/SER (Pi, To, Pd)  ADC (Ba)  VCO (Pd,To)  High Speed SLVS (Pv, To, Pi)  Control and command Interface (Pi, Ba)  Readout Interface (Pi,Ba)  Clock Driver/Receiver (Pv)  2) Test degli IP-block realizzati, irraggiamento e test per SEU L. Demaria - CHIPIX65 41

42 Attivita per il 2015 (3) Elettronica digitale  Sviluppo elettronica digitale (Pi, To, Mi, Ba)  per pixel matrix INFN  contributo ad eventuale matrice pixel di RD53 (shared)  Continua il contributo allo sviluppo di VEPIX53 in RD53 (Pg)  3) Sviluppo test board, carrier e firmware per test della pixel matrix (Pi,To) Elettronica Analogica  Caratterizzazione elettronica di VFE, prima e dopo irraggiamento. (Pv,To)  Disegno architetture analogiche per pixel matrix (Pv, To) L. Demaria - CHIPIX65 42

43 Attivita’ per il 2015 (4) Chip Integration  Preparazione di sottomissioni per i disegni di IP-block disegnati da CHIPIX65 (almeno 2 blocchi da 2x2mm 2 ).  Sottomissione condivisa con RD53 di IP-block INFN  Sottomissione di una prima piccola pixel matrix INFN (circa 3x4 mm 2 ) a metà anno  Sottomissione di una pixel matrix in sharing con RD53 a fine anno. L. Demaria - CHIPIX65 43

44 Milestones per 2015 Queste milestones fanno riferimento a quelle descritte nel Project Proposal del 2013 ed aggiornate.  Test of first IP-blocks 1-4-2015  Measurement of SEU rate with SRAM1-5-2015  Test of small pixel array1-10-2015  Definition of Very Front End analog architectures 1-12-2015  Test of all IP-block prototypes1-12-2015 L. Demaria - CHIPIX65 44

45 Richieste Finanziare per 2015 L. Demaria - CHIPIX65 45 In particolare Le richieste indivise

46 Conclusioni L. Demaria - CHIPIX65 46 Primi 6 mesi molto positivi per CHIPIX65 Layout in TSMC 65nm in 5 sedi su 6. Con NDA approvato, da settembre TUTTE le sedi potranno lavorare con 65nm Ottimo stato di avanzamento in IP-block e VFE- analogica: prima sottomisisone Ottobre 2014 Contributo a RD53 importante e presenza visibile dell’INFN Per il 2015 bisogna progredire in elettronica digitale complessa e sintetizzabile e sul top-level del chip: Importante sottomettere una small pixel array concepita completamente dall’INFN

47 BACKUP SLIDES L. Demaria - CHIPIX65 47

48 Focused R&D: Pixel Upgrades  Phase1 upgrades: Additional pixel layer, ~4 x hit rates  ATLAS: Addition of inner B layer with new 130nm pixel ASIC (FEI4)  CMS: New pixel detector with modified 250nm pixel ASIC (PSI46DIG)  Phase2 upgrades :  Installation: ~ 2022  Final CHIP ready for ~2017-18  Relies fully on significantly improved performance from next generation pixel chips CMS & ATLAS phase 2 pixel upgrades ATLAS Pixel IBL CMS Pixel phase1 100MHz/cm 2 4 00MHz/cm 2 1-2G Hz/cm 2 L. Demaria - CHIPIX65 48

49 Phase 2 pixel challenges  ATLAS and CMS phase 2 pixel upgrades very challenging  Very high particle rates: 500MHz/cm 2  Hit rates: 1-2 GHz/cm 2 (16 higher than current pixel detectors)  Smaller pixels: ¼ - ½ (25 – 50 um x 100um )  Increased resolution  Improved two track separation (jets)  Increased readout rates: 100kHz -> 1MHz  Low mass -> Low power Very similar requirements (and unc ertainties) for ATLAS & CMS  Unprecedented hostile radiation: 10MGy(1Grad), 10 16 Neu/cm 2  Hybrid pixel detector with separate readout chip and sensor.  Phase2 pixel will get in 1 year what we now get in 10 years  Participation in first/second level trigger ? A.40MHz extracted clusters and shape (outer layers) ? B.Region of interest readout for second level trigger ?  Very complex, high rate and radiation hard pixel readout chips required L. Demaria - CHIPIX65 49

50 PMOS Radiation effects 65nm 50 Transconductance Vt shift L. Demaria - CHIPIX65

51 RD53 WG1 (Radiation test/qualification): Summary CERN: pixel detector (to be used as the CLIC vertex detector, 65 nm technology) CERN: 10-keV X ray (CERN), till 1 Grad(SiO 2 ), 20 ºC annealing CERN: Ring oscillator & Shift register & SRAM (65 nm technology) CERN: 10-keV X ray (CERN), till 1 Grad(SiO 2 ), 100 ºC annealing At doses > 200 Mrad(SiO2), severe degradation can be observed. Big variation for front- end gain (left), ToT gain (right) and basic structures (switch, current mirror). Decrease in current and frequency of ring oscillator (left); Variation in supply current of other blocks (right).

52 RD53 WG1 (Radiation test/qualification): Outlook CERN: Annealing studies on Ring oscillator & Shift register & SRAM CPPM: New test interface and software. Hardware compatible to low temperature operation at CERN X-ray machine Padova: 10-keV X ray irradiation of 65 nm CERN test structures Setup of low temperature operation at Padova 3-MeV proton environment Fermi lab: Data analysis and annealing tests of 65 nm transistors (2-week Co-60 γ ray irradiation just finished) Others… L. Demaria - CHIPIX65 52

53 Top level WG  Global architecture and floor-plan issues for large mixed signal pixel chip  Convener: Maurice Garcia-Sciveres, LBNL  Activities and status  Global floorplan issues for pixel matrix  50x50um 2 – 25x100um 2 pixels with same pixel chip  ATLAS – CMS has agreed to initially aim for this  Global floor-plan with analog and digital regions  Appropriate design flow  Column bus versus serial links  Simplified matrix structure for initial pixel array test chips  Plans  Submission of common simplified pixel matrix test chips  Evaluation of different pixel chip (digital) architectures  Using simulation frameworks from simulation WG.  Final integration of full pixel chip  Bonn, LBNL,,,, 53 L. Demaria - CHIPIX65

54 Simulation/verification WG  Simulation and verification framework for complex pixel chips  Convener: Tomasz Hemperek, Bonn  Activities and status  Simulation framework based on system Verilog and UVM (industry standard for ASIC design and verification)  High abstraction level down to detailed gate/transistor level  Benchmarked using FEI4 design  First basic version of framework available on common repository  Internal generation of appropriate hit patterns  Used for initial study of buffering architectures in pixel array  Integration with ROOT to import hits from detector simulations and for monitoring and analysing results.  Plans  Refine/finalize framework with detailed reference model of pixel chip  Import pixel hit patterns from detector Monte-Carlo simulation  Modelling of different pixel chip architectures and optimization  Verification of final pixel chip  Bonn, CERN, Perugia 54 Buffer occupancy comparison between simulation and analytical statistical model L. Demaria - CHIPIX65

55 Analog WG  Evaluation, design and test of appropriate low power analog pixel Front-Ends  Convener: Valerio Re, Bergamo/Pavia  Activities and status  Analog front-end specifications  Planar, 3D sensors, capacitance, threshold, charge resolution, noise, deadtime,,  Alternative architectures –implementations to be compared, designed and tested by different groups  TOT, ADC, Synchronous, Asynchronous, Threshold adjust, Auto zeroing, etc.  Design / prototyping of FE’s ongoing  Plans  Prototyping and test (with radiation) different FEs  Some FEs have already been prototyped  Others will be prototyped after the summer  Test, comparison and choice of most appropriate FE(s)  Bergamo-Pavia, Bonn, CERN, CPPM, Fermilab, LBNL, Prague IP/FNSPE-CTU, Torino. 55 Krummenacher – TOT examples

56  1) I/O: Evaluation and definition of I/O protocols supporting 2Gbps or higher serial links, command based triggering up to 1MHz rate and minimum dead-time.  - 80Mbps or higher serial input, with command decoder to configure and operate the chip. Evaluation of a slow control protocol.  Command and Clock should be encoded on a single line.  - 2Gbps Serial Output links will require to evaluate different output data formats and compression alternatives.  - A duplex solution where all I/O takes place on a single serial connection should be considered. Investigation of link redundancy schemes to be eventually used on less data demanding layers.  2) Interfaces: Evaluation of compatibility with defined interfaces such as LPGBT.  3) IP blocks related to I/O: interface driver, clock recovery, clock multiplier methods, LVDS driver and receivers. [Work to be shared with the IP group]  4) Off chip connectivity: Calculation, Simulation and Test of transmission performance with realistic interconnects. I/O should not stop at the chip pads but extend to the system immediately outside the chip. High speed cables and protocols and even test interfaces. Therefore we should develop a specification for the system around it and a test setup. CHIPIX65 I/O group Responsabile R. Beccherle

57 Project TimeLine (1) N. Demaria - CHIPIX65 57

58 Project TimeLine (2) N. Demaria - CHIPIX65 58

59 TSMC / CERN Contract L. Demaria - CHIPIX65 59

60 L. Demaria - CHIPIX65 60