Scaricare la presentazione
La presentazione è in caricamento. Aspetta per favore
1
Online U. Marconi Milano, 21/9/2015 1
2
~ 9000 optical link 40 MHz PCIe based readout 30 MHz × 100 kB/evt 5 Gb/s, 300 m long fibres from the FEE directly to the Event Builder n ~ 30 MHz × 20 ms ~ 6 × 10 5 HLT threads 2 CERN-LHCC-2014-016 Event Builder
3
PCIe40 Contributo INFN: soluzione basata su protocollo PCI Express Modifica della board AMC40. Nuova FPGA. 3
4
PCIe40 Primo prototipo Aprile 2015. – FPGA Arria10 ES1: PCIe Gen2 Secondo prototipo Giugno 2015 – FPGA Arria10 ES2: Pcie Gen3 4
5
EB server 5
6
Event builder node 6 PCIe40 Event Building Network Interface Event Building Network Interface data from the detector ~ 100 Gb/s to the event builder Dual-port IB FDR – 110 Gb/s from the event builder events that are being built on this machine opportunity for doing pre-processing of full event here to the HLT empty DDR3 40-50 GB/s Half duplex 2x50 GB/s Full duplex DDR3 40-50 GB/s Half duplex
7
7
8
Event builder Collaborazione: INFN-BO, CNAF, CERN Sviluppo del modello di Event Building Test su farm effettuati usando protocolli MPI e InfiniBand verbs. 8
9
Cineca cluster bandwidth 9
10
Test MPI Presentati da A. Falabella:“13th Pisa Meeting on Advanced Detectors”. Problema MPI: fault tolerance 10
11
Bandwidth vs n. of nodes IB verbs 33.87 Gb/s 33.46 Gb/s 30.43 Gb/s 27.55 Gb/s Matteo Manzali LHCb week Bologna 14-18 Settembre 2015 11
12
Bandwidth vs n. of nodes IB verbs 25.29 Gb/s 24.98 Gb/s 12
13
Gara PCIe40 Market survey: 22 aziende Aziende italiane in gara: 5 o 6 13
14
Readout board Progetto originario: schede di readout AMC40 su crate ATCA. FEE 14
Presentazioni simili
