ATLAS calorimeter system barrel EC forward hadronic Scintillator LAr Em

ATLAS LAr: 3 cryostats Cold and filled with Lar ECA: In stable conditions since mid March 07 ATLAS LAr: 3 cryostats ECC Cold In stable conditions up to end Nov Now empty Barrel Cold and filled with Lar In stable conditions since Jun 06 barrel EC forward Hadronic Fe-Scintillator (tiles) Cu-Lar (plates) Cu, W-Lar (rods) em Pb-Lar (accordion) Pb-Lar (accordion) presampler LAr - LAr Calorimeters: EM Barrel : (||<1.475) EM End-caps : 1.4<||<3.2 Hadronic End-cap: 1.5<||<3.2 Forward Calo: 3.2<||<4.9 ~190K readout channels

Storicamente impegno di Milano sulla calorimetria EM Pb/LAr con geometria ad accordion (ma non solo) E tdrift =450 ns A t

Phase Milano involvement Design Early R&D, participation to RD3: electrodes, GaAs (cold) preamps Calo prototypes Early RD3 prototypes (barrel, EC); 2-m prototype Test beams Test beam of RD3 prototypes and data analysis Analysis of Module 0 data: uniformity of response (2000) Analysis of 4 production modules: energy calibration, signal reconstruction, uniformity of response (2001-2002) Procurement, Testing & equipping Electrode activity (up to Nov 2002): Follow-up of the electrode production at factory (CH) Construction and installation of electrode HV test station at factory (for ALL electrodes: barrel+endcap) Test and equipping in Milano of half of the barrel electrodes (2048): HV test:  integrity of the dielectric insulation RC test:  continuity of copper traces, correct etching  acceptable values of silk-screened resistors Follow-up of production of pre-amp at factory (I): 50% of all warm PA (barrel, EC). Development of test procedures and installation of test set-up at factory. Test and repair in our lab. Commissioning at assembly site TDR tests of all calibration lines of EM barrel and EC calorimeters HV tests of the assembled detector at warm and cold Design, construction and installation of services for endcap calorimeters A and C

Talks in next meetings Talks in next meetings Phase Milano involvement Commissioning in the pit, cosmic run HV tests and operations, writing of HV control software; integration in Central Atlas DCS SW commissioning Electronics calibration: signal reconstruction (up to 2004) ETMiss reconstruction and calibration Electron/photon energy calibration Tau reconstruction Commissioning w/ beam Run operation Physics analysis (di-)photon physics; Hgg Ztt; H/Att Upgrade for SLHC Evaluation of SiGe technology, and circuit built with it, in view of the re-design/replacement of the Liquid Argon calorimeter front-end electronics (FEB) Talks in next meetings Talks in next meetings

Da sempre il canale Hgg e’ il canale benchmark (assieme a HZZ(*)4e, Il gruppo ha da lungo tempo fatto molto lavoro nell’ambito della fisica dell’Higgs, SM e MSSM. SM Higgs: Hgg Da sempre il canale Hgg e’ il canale benchmark (assieme a HZZ(*)4e, soprattutto se H<2MZ) per la calorimetria EM ad LHC. Se l’Higgs e’ di bassa massa, questo canale rimane uno dei canali piu’ importanti per MH<150 GeV (soprattutto se si vuole mantenere un po’ di cautela rispetto ai canali VBF) Calorimetria elettromagnetica Performance a test beam Simulazioni H DC1 Calibrazione elettronica Simulazioni H CSC Calibrazione energia e/g Simulazioni FDR Studio fotone singolo (PDF), 2g QCD production Analisi canale Hgg

MSSM H: A/H Storicamente canale benchmark per le prestazioni di ATLAS per la ricostruzione di ETmiss (canale benchmark per l’intero sistema calorimetrico di ATLAS) e t Performance di ETmiss t identification Algoritmi per la identificazione di t adronici: calorimetro, tracking Ricostruzione e calibrazione di ETmiss Campione di controllo: Z→tt Analisi di H/A→tt

Lar HV system Hardware set-up (5 racks): 20 crates, ~150 HV modules produced by Iseg GmbH ~5000 channels The system serves all Lar calorimetry system (barrel, EC and forward; barrel and EC presamplers; barrel and EC purity monitors) Great knowledge of all hardware aspects of the system (Iseg modules, cables, interlock system) Hardware provided by : Wuppertal, CERN, Stockolm (+ Dresden) and Helmut Braun (Wuppertal) responsible. Milano joined the project beginning 2003 with the responsibility to develop the software. 100% responsible for all HV software

DCS Architecture DSS LHC Magnet CERN Tile CIC Pixel SCT TRT MDT TGC DIP WAN Magnet CERN DCS_IS Operator Interface Data Viewer Alarm Status Web LAN Tile CIC Pixel SCT TRT MDT TGC RPC CSC LAr OPC Cooling Racks Environ ELMB Temp HV FE Crates HEC LV Purity Front-End Systems LCS USAL1 LCS USAL2 LCS US15 LCS SDX1 LCS 2 LCS 3 LCS 4

6 PC to control the whole HV system EMBPS EMECPS EMEC hospital CC EMB EMB hospital Purity mon HEC -A FCAL-A HEC-C FCAL-C EMEC-A EMEC-C pcatlarhv1 pcatlarhv7 pcatlarhv3 pcatlarhv5 pcatlarhv2 pcatlarhv6 ID=59 ID=63 ID=57 ID=61 ID=58 ID=62 ECA barrel ECC 6 PC to control the whole HV system We have to control, maintain, upgrade and install software (standard and our software) on all 6 machines

LAr HV interlock review, 21/10/2007 ...to Iseg modules... We write software at two levels: Base software to control the modules via PC and for low level settings and monitoring Software to integrate our system in the rest of the ATLAS DCS. Communicate with the higher levels of the DCS systems. Especially for point 2, we use software tools developed by CERN IT-CO-BE or ATLAS central DCS. Main integration elements: Finite State Machine Alarms Condition DB write-out (Oracle/COOL) 2-channel Peak PCI CAN OPC server PVSS project HV PC Display in CR LAr HV interlock review, 21/10/2007

Integration performed during the M1-M5 weeks: All review successfully passed so far, all subsystems are now integrated Future plans: Systems are integrated but there are a lot of various issues still to be fixed, improved,… To be done: Condition DB: write-out of voltages and currents into COOL for offline use Configuration DB: download of preset configuration into modules Full usage of actions (ON, OFF, Ramp, Reset) into FSM Improvement of interlocks We need to be ready for start of run and need to provide a person to follow up the system when the first collisions will occur Today I am the only physicist “authorized” to ramp up/down the barrel EM and the only replacement for the other two physicists that operate HEC/FCAL and EMEC. Need to: Clean-up the programs and make them easier to use by semi-experts Instruct other physicists (Milano and other institutes) to operate the calorimeter

The Milestones Weeks give a first taste of the excitement we will enjoy in less than one year from now… The value of these global commissioning periods cannot be stressed enough CERN, 8-Oct-2007

Milano set-up One Iseg crate + 2 modules (same as the ones used in ATLAS) One 32 ch 2500 V/200 mA new generation Iseg module One 16 ch 2500 V/3 mA Used to perform special tests that it is not possible to do at CERN as all the modules are connected to the calorimeter Now performing the following tests: performance of the new modules Stability with time of the hi-current modules Hi-current module New generation Iseg module

Run tasks The tasks where we plan to contribute follow the current activities of the group: Lar tasks: HV activities clearly will have a large impact: HV expert, HV test set-up, DCS expert Data preparation: e/g calibration, ETmiss calibration

R&D per SLHC Argomenti di interesse (cfr. WG del GR1): elettronica FE, HV per SLHC Il gruppo di Milano ha aderito ad una proposta di R&D generale su elettronica FE in SiGe: "Evaluation of Silicon-Germanium (SiGe) Bipolar technologies for use in an upgraded ATLAS detector“, ATL-PA-MN-0006, 15/06/06) gia’ sottoscritta da varie istituzioni (BNL, S. Cruz, Barcellona, IN2P3, Penn) recentemente approvata dall’ ATLAS EB Milano interest will be mostly focused on studying the SiGe technology, and circuit built with it, in view of the re design/replacement of the Liquid Argon calorimeter FE electronics for the SLHC, for which a good analog process is essential. A preliminary architecture of a new LAr front-end electronics is described in an EOI being prepared by LAR

R&D per SLHC Nel 2008 il gruppo di Milano vorrebbe iniziare lo Sviluppo di Elettronica di Front-End : Caratterizzazione di dispositivi Bi-CMOS in SiGe (IBM e AMS) attraverso misure statiche, di rumore e di resistenza alle radiazioni Progettazione di una “libreria” di circuiti con layout “radiation tolerant” - la tecnologia SiGe e’ divenuta recentemente disponibile anche nei programmi EUROPRACTICE e MOSIS Sarebbe auspicabile un inizio di questa attivita’ nel 2008 in collaborazione con BNL e Orsay che hanno gia’ iniziato attivita’ simili nel 2007

Attuale Architettura della FEB La presente architettura e’ basata su: Architettura complessa che fa uso di 13 differenti ASICs Pipeline analogica (SCA) Somme analogiche sulla FEB digitalizzate da una Tower Builder Board e trasmesse otticamente al L1 (per mantenere una L1 latency ~2.5s) Grande sforzo per ridisegnare l’intera FEB rad hard

Possibile nuova architettura E’ una proposta che potrebbe ancora cambiare La nuova baseline si basa sull’idea di digitalizzare tutti i segnali il prima possibile Occorre avere ADC veloci sulla FEB per evitare la pipeline analogica on-detector Occorre ridurre al minimo la potenza dissipata nella fase di digitalizzazione esempio: assumendo che il 50% della potenza in una FEB sia dovuta agli ADC, e mantenendo costante la potenza globale per FEB a circa 100 Watt  ~100*0.5/128 ~0.4W/ADC. E’ possibile? LVL1 (digital) pipeline potrebbe avvenire ‘off detector’ se saranno disponibili link ottici veloci (strategia ancora tutta da verificare) La selezione del guadagno potrebbe avvenire prima (come in figura) o dopo l’ADC Occorre decidere quale tecnologia usare per l’upgrade della parte analogica  SiGe sembra essere una buona opzione