TMS320C6000 Instruction Set

2 'C6xx Instruction Set - Operands ADD.L1 A0, A1, A2 ADD.L2 -5, B3, B4 ADD.L1 A2, A3, A5:A4 ADD.L1 A2, A5:A4, A5:A4 ADD.L2 3, B9:B8, B9:B8

3 'C6xx Instruction Set - Cross Path ADD.L2x A0,A1,B2 MPY.M1x A0,B6,A9 SUB.S1x A8,B2,A8 ADD.L1x A0,B0,A2 ADD.L2x A0,A1,B2 MPY.M1x A0,B6,A9 SUB.S1x A8,B2,A8 ADD.L1x A0,B0,A2 LDW.D1T2 *A0,B5 STW.D2T1 A5,*B0 LDW.D1T2 *A0,B5 STW.D2T1 A5,*B0

4 'C6xx Instruction Set Parallel Operation ADD.L2x A0,A1,B2 | | MPY.M1x A0,B6,A9 SUB.S1x A8,B2,A8 ADD.L1x A0,B0,A2 ADD.L2x A0,A1,B2 | | MPY.M1x A0,B6,A9 SUB.S1x A8,B2,A8 ADD.L1x A0,B0,A2 LDW.D1T2 *A0,B5 || STW.D2T1 A5,*B0 LDW.D1T2 *A0,B5 || STW.D2T1 A5,*B0 L1 S1 M1 D1 L2 S2 M2 D2

5 Arithmetic ABS ADD ADDA ADDK ADD2 MPY MPYH NEG SMPY SMPYH SADD SAT SSUB SUB SUBA SUBC SUB2 ZERO Program Ctrl B IDLE NOP Logical AND CMPEQ (=) CMPGT (>) CMPLT ( >) SSHL XOR Data Mgmt LDB/H/W MV MVC MVK MVKL MVKH MVKLH STB/H/W Bit Mgmt CLR EXT LMBD NORM SET Note: Refer to the 'C6000 CPU Reference Guide for more details. 'C62x Instruction Set (by category) Aritmetica di saturazione Se utilizzassi la classica aritmetica di arrotondamento quando, ad esempio in un procedimento di incremento di colore, giungessi al limite di rappresentazione di un dato un ulteriore incremento determinerebbe un overflow, con il numero che raggiungerebbe erroneamente il limite opposto. Quando io sommo invece ad esempio due valori a 32 bit che raggiungono un valore eccedente i limiti di rappresentazione, avrei semplicemente bisogno di indicare che ho raggiunto il valore massimo rappresentabile. Questo è un evento particolarmente frequente in applicazioni multimediali (ad esempio nei valori di colore dei pixel), in cui laritmetica di saturazione è appositamente preposta. Integer Addition Using Signed 16-Bit Constant Integer Addition Using Addressing Mode Two 16-Bit Integer Adds on Upper and Lower Register Halves if (cond) {((lsb16(src1) + lsb16(src2)) and FFFFh) or ((msb16(src1) + msb16(src2)) dst} else nop Conditional Integer Subtract and Shift Used for Division if (cond) {if (src1 – src2 >= 0) ( (src1–src2) dst else src1 dst} else nop Signed or Unsigned Integer Multiply 16 lsb x 16 lsb Signed or Unsigned Integer Multiply 16 msb x 16 msb

6 'C62x Instruction Set (by unit).S Unit MVKLH NEG NOT OR SET SHL SHR SSHL SUB SUB2 XOR ZERO ADD ADDK ADD2 AND B CLR EXT MV MVC MVK MVKL MVKH.M Unit SMPY SMPYH MPY MPYH.L Unit NOT OR SADD SAT SSUB SUB SUBC XOR ZERO ABS ADD AND CMPEQ CMPGT CMPLT LMBD MV NEG NORM.D Unit STB/H/W SUB SUBA ZERO ADD ADDA LDB/H/W MV NEG Other IDLENOP Note: Refer to the 'C6000 CPU Reference Guide for more details. TMS320C 62x /C 64x /C 67x Fixed-Point Instruction Set

7 ' C67x : Superset of Floating-Point No Unit Used IDLENOP.S Unit NEG NOT OR SET SHL SHR SSHL SUB SUB2 XOR ZERO ADD ADDK ADD2 AND B CLR EXT MV MVC MVK MVKL MVKH ABSSP ABSDP CMPGTSP CMPEQSP CMPLTSP CMPGTDP CMPEQDP CMPLTDP RCPSP RCPDP RSQRSP RSQRDP SPDP.L Unit NOT OR SADD SAT SSUB SUB SUBC XOR ZERO ABS ADD AND CMPEQ CMPGT CMPLT LMBD MV NEG NORM ADDSP ADDDP SUBSP SUBDP INTSP INTDP SPINT DPINT SPTRUNC DPTRUNC DPSP.M Unit SMPY SMPYH MPY MPYH MPYLH MPYHL MPYI MPYID MPYSP MPYDP MPYI MPYID.D Unit NEG STB(B/H/W) SUB SUBAB (B/H/W) ZERO ADD ADDAB(B/H/W) ADDAD LDB(B/H/W) LDDW MV Note: Refer to the 'C6000 CPU Reference Guide for more details. (by unit) 32-Bit Integer Multiply – Result Is Lower 32 Bits 32-Bit Integer Multiply – Result Is Lower 64 Bits

8 C62x: Dual 32-Bit Load/Store C64x: Dual 64-Bit Load/Store C67x: Dual 64-Bit Load/32-Bit Store Instruction Decode Instruction Dispatch Instruction Fetch Control Registers Interrupt Control Emulation Registers (B0 - B15) D2 + M2 X S2 + + L2 + Registers (A0 - A15) D1 + M1 X S1 + + L1 + Advanced Instruction Packing Advanced Emulation Registers (B16 - B31)Registers (A16 - A31) + x x x x X x x x x X Superset of Floating-Point

9 'C64x: Superset Fixed-Point of C62x Data Pack/Un PACK2 PACKH2 PACKLH2 PACKHL2 PACKH4 PACKL4 UNPKHU4 UNPKLU4 SWAP2/4 Dual/Quad Arith ABS2 ADD2 ADD4 MAX MIN SUB2 SUB4 SUBABS4 Bitwise Logical ANDN Shift & Merge SHLMB SHRMB Load Constant MVK (5-bit).L.D.S.M Bit Operations BITC4 BITR DEAL SHFL Move MVD Average AVG2 AVG4 Shifts ROTL SSHVL SSHVR Multiplies MPYHI MPYLI MPYHIR MPYLIR MPY2 SMPY2 DOTP2 DOTPN2 DOTPRSU2 DOTPNRSU2 DOTPU4 DOTPSU4 GMPY4 XPND2/4 Mem Access LDDW LDNW LDNDW STDW STNW STNDW Load Constant MVK (5-bit) Dual Arithmetic ADD2 SUB2 Bitwise Logical AND ANDN OR XOR Address Calc. ADDAD Data Pack/Un PACK2 PACKH2 PACKLH2 PACKHL2 UNPKHU4 UNPKLU4 SWAP2 SPACK2 SPACKU4 Dual/Quad Arith SADD2 SADDUS2 SADD4 Bitwise Logical ANDN Shifts & Merge SHR2 SHRU2 SHLMB SHRMB Compares CMPEQ2 CMPEQ4 CMPGT2 CMPGT4 Branches/PC BDEC BPOS BNOP ADDKPC