Muon System Electronics Upgrade Meeting Summary

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1 Muon System Electronics Upgrade Meeting Summary
Alessandro Cardini / INFN Cagliari

2 A. Cardini / INFN Cagliari
Roma, October 10, 2014 A. Cardini / INFN Cagliari

3 nSYNC Architecture TDC + Histogram builder:
4 bit TDC (1.5 ns 40 MHz) 16 bins of 224 entries each. The counts stop when any of the bins saturates. Dead time free in hit capture. Muon Trigger TELL40 Interface: Sends synchronized hits every machine cycle (40 MHz). Prog. buffer depth to guarantee the synchronization between different nSYNC sending data through the same GBT TDC ZS: Zero Suppression of TDC’s data not related to hit events. TDC TELL40 Interface: Sends synchronized ZS TDC data every machine cycle (40 MHz). I2C Interface: Configure through the ECS. Triple-voted configuration S. Cadeddu - INFN Cagliari Roma - 08/10/14

4 nSYNC: alcuni punti (quasi) fermi
Tecnologia: Al momento UMC 130 nm In attesa di notizie/decisioni dal CERN sulla TSMC 130 nm 48 canali 1 GBT per nSYNC => 4 link indipendenti per nODE 1 GBT_TFC per nODE 1 GBT_SCA per nODE Clock 40 MHz di sistema (da dove?) 80/160/320 MHz per interfacce GBT (quale frequenza?; Il clock generato dal GBT stesso?) Interfaccia ECS I2C o SPI (?) S. Cadeddu - INFN Cagliari Roma - 08/10/14

5 nODE NOW nSYNC @ 48 channels 4 GBTx for hit+ TDC data
Slave GBT Widebus 112 bits 16 bits for header 48 bits for data hits 48 bits for TDC data 12 out of 48 channels (25% occupancy) Truncation event by event 1 GBTx forTFC/ECS MasterGBT 1 GBT-SCA 2 VTTx 1 VTRx nSYNC 48Input ch Trig hit TDC out VTTx GBTx ECS VTRx GBT SCA

6 GBTx clock Livelli logici usati Input clock SLVS e CMOS Power-up
Ha bisogno di un reference clock per effettuare la procedura di startup del chip e di inizializzazione del link 3 opzioni Low-jitter external clock  opzione consigliate per i GBT slave External clock+internal XPLL  opzione consigliate per i GBT slave Internal XPLL in XOSC mode (usa un quarzo incapsulato nel package)  opzione consigliate per i GBT master La scelta viene effettuata tramite un pin esterno tra opt. 1 e 2/3 e con un registro interno tra opt.2 e 3 Alla fine della procedure di power-on ( 2ms) vengono generati dei segnali di ready rxRdy (receiver ready): the receiver part of the GBTX is ready for operation txRdy (transmitter ready): the transmitter part of the GBTX is ready for operation Dopo l’init del link ottico il clock del GBTx è sincrono con: il clock estratto dai dati del link ottico se il GBTx lavora in modalità duplex il reference clock se il GBTx lavora in modalità Simplex-TX

7 GBTx clock Occorre scegliere uno schema che
Garantisca la massima flessibilità Minimizzi il numero di input verso l’nSYNC Nota: bisogna capire se/come sincronizzare il clock con i comandi del TFC

8 GBTx wide frame format 4 bit Header (H) field (2 types)
2 bit Internal Control (IC) field used to control and monitor the GBTX operation Its use is strictly reserved for the GBTX control. 2 bit External Control (EC) field to implement a slow control channel (e.g. for the GBT-SCA) its use is not restricted to this application and can be used for generic data transmission applications. 112 bit Data (D) field for generic transmission of data

9 TFC+ECS Recommended communication links within a FE module

10 ECS interface List of mandatory monitoring counters in an FE module

11 A. Cardini / INFN Cagliari
PCIe40 Firmware In Rome2 the PCIe40 firmware development environment is ready Minidaq boad expected by the end of the month – currently under test in Marseille Then: start Minidaq standalone testing Useful environment to start developing new ECS software (M. Carletti) Will purchase few GBT test board (with VTTRx, GBT & GBT-SCA) MiniDaq MiniDaq GBT test b. Roma, October 10, 2014 A. Cardini / INFN Cagliari

12 New Service Board Module
(multiple GBT old Backplane) SCL SDA_IN SDA_OUT Test/Pulse RESET Long line I2C FE converter 1 12 x I2C lines 2 Flash FPGA Test/pulse 3 E-Link 80 Mbits/s Long line I2C FE converter 1 3x LVDS I2c each ELMB GBT-SCA 2 3 Test/pulse Long line I2C FE converter I2C 1 2 test pulse logic CLK40 3 Test/pulse BC Pulse Long line I2C FE converter 1 IGLOO2 Actel Flash FPGA 2 ttl/lvds converter Test/pulse 3

13 New Pulse Distribution Module single GBT
Fiber 16 x E-Link 80Mbits/s GBT 40 MHz Machine CLK 2 LVDS I2C BC counter BC Pulse Generator 2 LVDS IGLOO2 Actel Flash FPGA Sync BC pulse 13

14 New Custom Backplane 80 Mbits/s E-LINK P D M S L O T
New Custom Backplane routing 80 Mbits/s E-Link Lines And Service line

15 LVDS Test of the new IGLOO2 Flash FPGA
Cardiacs Patch bypass lvds LVDS Test using IGLOO2 bypassing SB Service Board IGLOO2 Evaluation Board Microcontroller Board to drive standard I2C SB EB Igloo2 LVDS

16 Removing HW Muon LLT option
The final design of the nSYNC ASIC and of the nODE board depend also on how we are planning to implement the Muon LLT A SW-only muon LLT will allow an hardware simplification and an important money saving (fewer pins on the nSYNC, fewer optical link on the nODE) because we could remove the output lines to the LLT In addition, further changes to the current muon system layout are only possible in the case of a full software LLT Discussions have already started during an electronics upgrade meeting on June 27th, 2014; there are no opposition in principle (SW LLT is already the baseline) In Orsay we decided to approve this choice at next TB in December. A documents describing advantages/disadvantages will be prepared together with Julien C. Orsay, 16/09/2014 A. Cardini / INFN Cagliari