4DMPET M. G. Bisogni Preventivi INFN GV /07/2012

Sezioni INFN partecipanti  Pisa (M.G. Bisogni, A. Del Guerra, N. Marino, L. Fanucci, C. Saponara, R. Roncella, F. Baronti, G. Borgese, M.Morrocchi B. Liu)  caratterizzazione del modulo  Elettronica di Read-out  ASIC TDC alta risoluzione e protocollo di trasmissione FF-LYNX (DIIET)  Bari (F. Corsi, C. Marzocca, G. Matarrese)  ASIC Front-End  Perugia (G. Ambrosi, C. Santoni)  Caratterizzazione e test matrici e SiPM singoli  Integrazione e costruzione del modulo  Torino (C. Peroni, P.G. Cerello, R. Wheadon, F. Pennazio)  Simulazioni Monte Carlo  Compatibilita’ magnetica

Proposed layout  4DMPET block detector proposed layout  48 x 48 x 10 mm 3 LYSO slab  Minimize dead area between blocks  2 SIPM layers 16 x 16 pixel 3 mm pitch ->segmentation  The signals coming from the arrays of SiPMs are processed by custom Mixed-Mode Front-End ASICs.  Each ASIC contains a number of independent channels made up of preamplifier, shaper (filter), discriminators and Time to Digital Converters (TDC)  The energy information can be extracted by applying the Time Over Threshold (TOT): the time duration of the signal above threshold can be related to the energy released in the detector  The Front-End ASICs is controlled by a cluster processor  Handles the control signals and the transmission of filtered data to the back-end electronics.  Reduces to a minimum the bandwidth required towards the external data acquisition system.  Implements on the FPGA cluster processing algorithms such that only cluster position coordinates X, Y, time and TOT are transmitted. 3

Validation of the Montecarlo simulation  Simulation parameters are validated through the reproduction of different preliminary set-up made to study the SiPM and crystal performance. White slab INFN – Pisa 2 Na22 spectrum 3mm x 3mm SiPM (FBK-irst) LYSO 3mm x 3mm x 10mm painted white, coupled to the SiPM with optical grease Data acquisition with a Lecroy oscilloscope – 2GHz band, 2 Gsample/s 2 G. De Luca et al., Signal shape of a PET detector based on LSO:Ce,Ca crystals and SiPM, /11/2011 IEEE 2/28/12 ICTR-PHE

Mixed-mode readout ASIC  The analog front-end is simulated through a Simulink instrument. The signal obtained is a TOT signal, i.e. a binary signal in which the leading edge corresponds to the timestamp and its duration is proportional to the energy. 21/06/2012 5

Time to digital converter ASIC  Time to digital converter ASIC  The TDC is simulated with a C++ macro, the TOT signal edges are measured. The leading edge time is measured with a precision of 100 ps, while the trailing one with will be measured by the TDC with a precision of 400 ps, but at the moment only the 100 ps precision is implemented in the simulation. 6

Time to Digital Converter (TDC) Readout architecture 4321 from the front-end to the cluster processor  TOF timestamp: 100 ps  TOT timestamp: 400 ps  nominal σ LSB (TOF): 29 ps  dynamic range: ns  double hit res.: 70 ns  26 bit digital output word  other features:  total pulses count  missed event flag Ch# | flag | TOF | TOT | pulses cnt missed event output:

Time to Digital Converter (TDC) Readout architecture 4321 Rising and falling edge of events are measured by sampling:  8 bit systolic counter:  coarse time T c  T c LSB = 400 ps  4 stages delay-locked-loop:  fine time T f  T f LSB = 100 ps TOF = T c + T f (rising edge) TOT = T c (falling edge)

Spatial resolution (x and y)  Resolution along x RMS 1.6 mm FWHM 0.86 mm FWTM 2.5 mm 21/06/ DMPET collaboration – report on simulations

DOI resolution (z)  Resolution along z RMS 1.7 mm FWHM 1.4 mm FWTM 3.5 mm 21/06/ DMPET collaboration – report on simulations

TOF resolution (t)  RMS 660 ps FWHM 170 ps FWTM 600 ps  Sigma 140 ps 11

Workplan  Blocco da (chip da 4 canali ciascuno) vs blocco da (Detector proof of concept)  Cristalli e Detector board → Pisa (settembre)  Assembly dei SiPM e montaggio detector  Perugia, Pisa (settembre)  Chip FE → Bari (sottomissione a novembre)  Chip TDC → Pisa (sottomissione a ottobre)  Chipboard: a 1 chip per il test, a 4 chip per il modulo → Bari, Pisa  DAQ → Bari, Pisa, Torino  Cooling a 5°C → → investigare torino, Perugia, pisa

Workplan  Blocco da (chip da 64 canali ciascuno) vs blocco da   Cristalli → Pisa  Detector 1024 SiPM totali → Perugia  Detector board → Pisa  Chip FE/TDC: PICOSEC* (64 canali da sottomettere a Luglio 2012) → Torino  Chipboard → Torino  DAQ: 2 evaluation board da 512 canali l’una → Bari (1), Pisa (1)  Cooling a 5°C → investigare torino, Perugia, pisa

Manuel Rolo, LIP, Lisbona on behalf of PICOSECFP7 collaboration

Prototype data acquisition 4DMPET prototype ASICs (Bari-FE/Pisa-TDC) submission delayed 1 year  experimental data from existing electronics – Basic32 (Bari) Design of readout board and adaptation of Panda FPGA beam test DAQ Xilinx ML605 evaluation board (Virtex 6) Two FMC connectors => two Basic32 boards Control / readout via Gigabit Ethernet

Topix Topix control logic External Clock 160MHz External DACs External Counter Reset Control FIFOs Config RAM CPU Interface DAC control logic FPGA Microblaze CPU 100MHz Ethernet RAM Events FIFO CF Switch PC (LabVIEW) Firmware (VHDL)Hardware Software (C) Panda test beam DAQ system architecture Other boards Both firmware and software executable stored on CF, updatable via ethernet

Persone Ricercatori % BisogniM.G.100 Del GuerraA.40 MarinoN.100 BorgeseG.100 MorrocchiM.100 LiuB.100 FanucciL.30 SaponaraS.30 RoncellaR.30 BarontiF FTE/ 10 ric Tesi di Laurea: G. Pirrone

Richieste Finanziarie Richieste 2013 Consumi Detector board5000 Cristalli5000 Metabolismo5000 Missioni Interne Riunione collaborazione3000 Missioni Estero 2 Congressi4000 totale22000

Richieste supporto in sezione  Servizio AT: 0.3 FTE  Servizio Elettronico : progettazione PCB 1MU  Progettazione Meccanica: disegno supporti 1MU  Officina Meccanica: realizzazione supporti 1 MU

Progetti in corso: 4DMPET (INFN) ENVISION TOF-PET adroterapia (FP7) Hadronphysics (FP7) COST PET-MRI (FP7) INFIERI (FP7) Progetti sottomessi: PRIN anni