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CMOS VLSI Design1: IntroductionSlide 1 Microelettronica Anno Accademico 2006-2007 Prof. Adelio Salsano Presentazione e programma del corso.

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Presentazione sul tema: "CMOS VLSI Design1: IntroductionSlide 1 Microelettronica Anno Accademico 2006-2007 Prof. Adelio Salsano Presentazione e programma del corso."— Transcript della presentazione:

1 CMOS VLSI Design1: IntroductionSlide 1 Microelettronica Anno Accademico Prof. Adelio Salsano Presentazione e programma del corso

2 CMOS VLSI Design1: IntroductionSlide 2 OBIETTIVO Tecnologie, blocchi elementari e architetture per lanalisi e la sintesi di circuiti e sistemi microelettronici ALTERNATIVE Circuiti non programmabili Circuiti programmabili Circuiti dedicati Soluzioni miste Il corso fornisce le competenze necessarie per la valutazione delle prestazioni di circuiti e sistemi elettronici come prerequisito per la sintesi

3 CMOS VLSI Design1: IntroductionSlide 3 Notizie sul corso Orario Mercoledì 11,30Aula 9 Giovedì11,30Aula 7 Venerdì11,30Aula 12 Materiale didattico Diapositive lezioni N.H.E. Weste, D. Harris Principles of CMOS VLSI Design, Addison Wesley R. L. Geiger, P.E. Allen, N.R. Strader VLSIdesign techniques for analog and digital Circuits, Mac Graw Hill Int. Ed.

4 CMOS VLSI Design1: IntroductionSlide 4 PROGRAMMA DEL CORSO Introduzione Considerazioni generali Aspetti tecnici ed economici Richiami circuitali: –Inverter, NAND, NOR –Pass transistor, transmission gate –Latch, flip flop –Regole di progetto Il transistor MOS –Caratteristiche I-V –Caratteristiche C-V –Modelli delle capacità G,S,D –Effetti non ideali

5 CMOS VLSI Design1: IntroductionSlide 5 (segue Programma) Inverter CMOS – Caratteristiche in DC –Beta, rapporto dei beta, margini di rumore –Inverter dipendenti dal rapporto dei beta Inverter a pass transistor e tristate Modelli RC di ritardo Tecnologie CMOS: –Litografia,formazione del canale, ossidazione, contatti e metallizzazione –Regole di progetto Elementi circuitali: transistor, caoacità, resistenze, transistor bipolari, memorie

6 CMOS VLSI Design1: IntroductionSlide 6 (segue Programma) Stima delle prestazioni –Ritardi dei circuiti elementari: sforzo logico –Dissipazione di potenza –nterconnessioni –Margini progettuali Affidabilità e diagnostica dei circuiti integrati: –elettromigrazione, riscaldamento, latchup –guasti transitori e permanenti –testing on line e off line –modelli di guasto –design for testability

7 CMOS VLSI Design1: IntroductionSlide 7 (segue Programma) La simulazione circuitale: SPICE Logica a pass transistor Circuiti BICMOS Confronto tra le famiglie Logica statica e dinamica Sistemi digitali complessi: latch, flip flop, sincronizzazione –microprocessori, memorie, logica programmabile Circuiti e sistemi analogici: –Interruttori e resistenze attive –specchio di corrente –riferimenti di corrente e tensione –amplificatori invertenti e differenziali –amplificatore operazionale

8 CMOS VLSI Design1: IntroductionSlide 8 Brief History Till 1970 I.C. bipolar, afterwards MOSFET SSI1-100 MOS MSI MOS LSI MOS VLSI MOS ULSI> 10 6 MOS

9 CMOS VLSI Design1: IntroductionSlide 9 Brief History (cont.) 1958: First integrated circuit –Flip-flop using two transistors –Built by Jack Kilby at Texas Instruments 2003 –Intel Pentium 4 processor (55 million transistors) –512 Mbit DRAM (> 0.5 billion transistors) 53% compound annual growth rate over 45 years –No other technology has grown so fast so long Driven by miniaturization of transistors –Smaller is cheaper, faster, lower in power! –Revolutionary effects on society

10 CMOS VLSI Design1: IntroductionSlide 10 Vantaggi della tecnologia integrata Dimensioni: Fette di silicio (2003) fino a 12 pollici Velocità Consumo di potenza Dimensioni del sistema Costo del sistema Legge di MOORE: raddoppio ogni anno e mezzo del numero di componenti per chip CHIP

11 CMOS VLSI Design1: IntroductionSlide 11 MERCATO DEI CIRCUITI INTEGRATI

12 CMOS VLSI Design1: IntroductionSlide 12 COMPLESSITA MICRO INTEL

13 CMOS VLSI Design1: IntroductionSlide 13 FREQUENZE MICRO INTEL

14 CMOS VLSI Design1: IntroductionSlide 14 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors

15 CMOS VLSI Design1: IntroductionSlide 15 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)

16 CMOS VLSI Design1: IntroductionSlide 16 p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction

17 CMOS VLSI Design1: IntroductionSlide 17 nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor –Gate and body are conductors –SiO 2 (oxide) is a very good insulator –Called metal – oxide – semiconductor (MOS) capacitor –Even though gate is no longer made of metal

18 CMOS VLSI Design1: IntroductionSlide 18 nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: –P-type body is at low voltage –Source-body and drain-body diodes are OFF –No current flows, transistor is OFF

19 CMOS VLSI Design1: IntroductionSlide 19 nMOS Operation Cont. When the gate is at a high voltage: –Positive charge on gate of MOS capacitor –Negative charge attracted to body –Inverts a channel under gate to n-type –Now current can flow through n-type silicon from source through channel to drain, transistor is ON

20 CMOS VLSI Design1: IntroductionSlide 20 pMOS Transistor Similar, but doping and voltages reversed –Body tied to high voltage (V DD ) –Gate low: transistor ON –Gate high: transistor OFF –Bubble indicates inverted behavior

21 CMOS VLSI Design1: IntroductionSlide 21 Power Supply Voltage GND = 0 V In 1980s, V DD = 5V V DD has decreased in modern processes –High V DD would damage modern tiny transistors –Lower V DD saves power V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

22 CMOS VLSI Design1: IntroductionSlide 22 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain

23 CMOS VLSI Design1: IntroductionSlide 23 CMOS Inverter AY 0 1

24 CMOS VLSI Design1: IntroductionSlide 24 CMOS Inverter AY 0 10

25 CMOS VLSI Design1: IntroductionSlide 25 CMOS Inverter AY 01 10

26 CMOS VLSI Design1: IntroductionSlide 26 CMOS NAND Gate ABY

27 CMOS VLSI Design1: IntroductionSlide 27 CMOS NAND Gate ABY

28 CMOS VLSI Design1: IntroductionSlide 28 CMOS NAND Gate ABY

29 CMOS VLSI Design1: IntroductionSlide 29 CMOS NAND Gate ABY

30 CMOS VLSI Design1: IntroductionSlide 30 CMOS NAND Gate ABY

31 CMOS VLSI Design1: IntroductionSlide 31 CMOS NOR Gate ABY

32 CMOS VLSI Design1: IntroductionSlide 32 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

33 CMOS VLSI Design1: IntroductionSlide 33 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

34 CMOS VLSI Design1: IntroductionSlide 34 CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

35 CMOS VLSI Design1: IntroductionSlide 35 Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors

36 CMOS VLSI Design1: IntroductionSlide 36 Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Schottky Diode Use heavily doped well and substrate contacts / taps

37 CMOS VLSI Design1: IntroductionSlide 37 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line

38 CMOS VLSI Design1: IntroductionSlide 38 Detailed Mask Views Six masks –n-well –Polysilicon –n+ diffusion –p+ diffusion –Contact –Metal

39 CMOS VLSI Design1: IntroductionSlide 39 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well –Cover wafer with protective layer of SiO 2 (oxide) –Remove layer where n-well should be built –Implant or diffuse n dopants into exposed wafer –Strip off SiO 2

40 CMOS VLSI Design1: IntroductionSlide 40 Oxidation Grow SiO 2 on top of Si wafer –900 – 1200 C with H 2 O or O 2 in oxidation furnace

41 CMOS VLSI Design1: IntroductionSlide 41 Photoresist Spin on photoresist –Photoresist is a light-sensitive organic polymer –Softens where exposed to light

42 CMOS VLSI Design1: IntroductionSlide 42 Lithography Expose photoresist through n-well mask Strip off exposed photoresist

43 CMOS VLSI Design1: IntroductionSlide 43 Etch Etch oxide with hydrofluoric acid (HF) –Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

44 CMOS VLSI Design1: IntroductionSlide 44 Strip Photoresist Strip off remaining photoresist –Use mixture of acids called piranah etch Necessary so resist doesnt melt in next step

45 CMOS VLSI Design1: IntroductionSlide 45 n-well n-well is formed with diffusion or ion implantation Diffusion –Place wafer in furnace with arsenic gas –Heat until As atoms diffuse into exposed Si Ion Implanatation –Blast wafer with beam of As ions –Ions blocked by SiO 2, only enter exposed Si

46 CMOS VLSI Design1: IntroductionSlide 46 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

47 CMOS VLSI Design1: IntroductionSlide 47 Polysilicon Deposit very thin layer of gate oxide –< 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer –Place wafer in furnace with Silane gas (SiH 4 ) –Forms many small crystals called polysilicon –Heavily doped to be good conductor

48 CMOS VLSI Design1: IntroductionSlide 48 Polysilicon Patterning Use same lithography process to pattern polysilicon

49 CMOS VLSI Design1: IntroductionSlide 49 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

50 CMOS VLSI Design1: IntroductionSlide 50 N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing

51 CMOS VLSI Design1: IntroductionSlide 51 N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

52 CMOS VLSI Design1: IntroductionSlide 52 N-diffusion cont. Strip off oxide to complete patterning step

53 CMOS VLSI Design1: IntroductionSlide 53 P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

54 CMOS VLSI Design1: IntroductionSlide 54 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

55 CMOS VLSI Design1: IntroductionSlide 55 Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

56 CMOS VLSI Design1: IntroductionSlide 56 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain –Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of = f/2 –E.g. = 0.3 m in 0.6 m process

57 CMOS VLSI Design1: IntroductionSlide 57 Simplified Design Rules Conservative rules to get you started

58 CMOS VLSI Design1: IntroductionSlide 58 Inverter Layout Transistor dimensions specified as Width / Length –Minimum size is 4 / 2 sometimes called 1 unit –In f = 0.6 m process, this is 1.2 m wide, 0.6 m long

59 CMOS VLSI Design1: IntroductionSlide 59 Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip!


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