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1 Progettazione di circuiti e sistemi VLSI Anno Accademico 2011-2012 Prof. Adelio Salsano 6.3 e 8.3 Presentazione e programma del corso.

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Presentazione sul tema: "1 Progettazione di circuiti e sistemi VLSI Anno Accademico 2011-2012 Prof. Adelio Salsano 6.3 e 8.3 Presentazione e programma del corso."— Transcript della presentazione:

1 1 Progettazione di circuiti e sistemi VLSI Anno Accademico Prof. Adelio Salsano 6.3 e 8.3 Presentazione e programma del corso

2 2 Programma Cenni storici. Problematiche progettuali: costi, prestazioni, potenza. Tecnologie integrate CMOS: passi progettuali, regole di layout, packaging Richiami sui componenti elementari ideali e reali. Modelli SPICE del diodo, del transistor MOS e dei componenti passivi Interconnessioni, modelli RC. Modelli SPICE delle connessioni Nanotecnologie: aspetti tecnologici e modelli

3 3 Programma (segue) Circuiti digitali elementari: inverter CMOS e transmission gate. Caratteristiche statiche e dinamiche. Potenza, energia e ritardo dei circuiti elementari Porte logiche combinatorie. Logica statica e dinamica. Prestazioni e caratteristiche Circuiti logici sequenziali. Latch e registri. Pipeline Circuiti e sistemi digitali complessi e metodologie di implementazione: processori, PLA, FPGA, standard cell Memorie statiche e dinamiche. Memorie e non volatili

4 4 Programma (segue) Affidabilità e tolleranza ai guasti dei circuiti integrati. Circuiti integrati analogici: interruttori, riferimenti di corrente e tensione, specchi di corrente, amplificatori differenziali Strumenti per la progettazione di circuiti e sistemi: linguaggi descrittivi, i principali programmi di sintesi Progettazione custom, standard cell e componenti programmabili Progettazione ad alta affidabilità e/o basso consumo

5 5 Programma Esercitazioni (segue) Sono previste esercitazioni sui seguenti temi: Programmi simulazione (LTSpice…) Calcolo parametri Progettazione digitale RTL Progetto circuiti e sistemi FPGA e Xilinx Linguaggi descrittivi Progettazione FPGA

6 6 Notizie sul corso Esercitazioni Sono previste 25 ore di esercitazioni con luso di software di progetto e simulazione di componenti e circuiti prevalentemente digitali. Collaboratori Prof. Stefano Bertazzoni; Salvatore Pontarelli e Marco Ottavi Materiale didattico Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Circuiti Integrati Digitali: lottica del progettista, Pearson Prentice Hall R. L. Geiger, P.E. Allen, N.R. Strader VLSI design techniques for analog and digital Circuits, Mac Graw Hill Int. Ed. Diapositive lezione e esercitazioni

7 7 Notizie sul corso (segue) ORARIO Martedì 9,30 – 11,15 Aula C8 Giovedì 9.30 – Aula C8 Venerdì Aula C1 RICEVIMENTO STUDENTI Lunedì e giovedì 15 – 16.30

8 8 What is this course/book about? Introduction to digital integrated circuits. –CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. What will you learn? –Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability

9 9 The First Computer

10 10 first ENIAC - The first electronic computer (1946)

11 11 The Transistor Revolution First transistor Bell Labs, 1948

12 12 The First Integrated Circuits Bipolar logic 1960s ECL 3-input Gate Motorola 1966

13 13 Intel 4004 Micro-Processor transistors 1 MHz operation

14 14 Intel Pentium (IV) microprocessor

15 15 Moores Law He made a prediction that semiconductor technology will double its effectiveness every 18 months In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

16 16 Moores Law Electronics, April 19, 1965.

17 17 Evolution in Complexity

18 18 Transistor Counts 1,000, ,000 10,000 1, i386 i486 Pentium ® Pentium ® Pro K 1 Billion Transistors Source: Intel Projected Pentium ® II Pentium ® III Courtesy, Intel

19 19 Moores law in Microprocessors Pentium® proc P Year Transistors (MT) 2X growth in 1.96 years! Transistors on Lead Microprocessors double every 2 years Courtesy, Intel

20 20 Die Size Growth Pentium ® proc P Year Die size (mm) ~7% growth per year ~2X growth in 10 years Die size grows by 14% to satisfy Moores Law Courtesy, Intel

21 21 Frequency P6 Pentium ® proc Year Frequency (Mhz) Lead Microprocessors frequency doubles every 2 years Doubles every 2 years Courtesy, Intel

22 22 Power Dissipation P6 Pentium ® proc Year Power (Watts) Lead Microprocessors power continues to increase Courtesy, Intel

23 23 Power will be a major problem 5KW 18KW 1.5KW 500W Pentium® proc Year Power (Watts) Power delivery and dissipation will be prohibitive Courtesy, Intel

24 24 Power density Pentium® proc P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel

25 25 Not Only Microprocessors Digital Cellular Market (Phones Shipped) Units 48M 86M 162M 260M 435M Analog Baseband Digital Baseband (DSP + MCU ) Power Management Small Signal RF Power RF (data from Texas Instruments) Cell Phone

26 26 Challenges in Digital Design Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. …and Theres a Lot of Them! ?

27 27 Productivity Trends ,000 10, ,000 1,000,000 10,000, ,000 10, ,000 1,000,000 10,000, ,000,000 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1, Logic Transistor per Chip (M) ,000 10, ,000 Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity Complexity Courtesy, ITRS Roadmap

28 28 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But … –How to design chips with more and more functions? –Design engineering population does not double every two years… Hence, a need for more efficient design methods –Exploit different levels of abstraction

29 29 Design Abstraction Levels n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM

30 30 Design Metrics How to evaluate performance of a digital circuit (gate, block, …)? –Cost –Reliability –Scalability –Speed (delay, operating frequency) –Power dissipation –Energy to perform a function

31 31 Cost of Integrated Circuits NRE (non-recurrent engineering) costs –design time and effort, mask generation –one-time cost factor Recurrent costs –silicon processing, packaging, test –proportional to volume –proportional to chip area

32 32 NRE Cost is Increasing

33 33 Die Cost Single die Wafer From Going up to 12 (30cm)

34 34 Cost per Transistor cost: ¢-per-transistor Fabrication capital cost per transistor (Moores law)

35 35 Yield

36 36 Defects is approximately 3

37 37 Some Examples (1994) ChipMetal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer YieldDie cost 386DX 20.90$ %$4 486 DX $ %$12 Power PC $ %$53 HP PA $ %$73 DEC Alpha 30.70$ %$149 Super Sparc 30.70$ %$272 Pentium 30.80$ %$417

38 38 Reliability Noise in Digital Integrated Circuits i(t) Inductive coupling Capacitive couplingPower and ground noise v (t) V DD

39 39 DC Operation Voltage Transfer Characteristic V(x) V(y) V OH V OL V M V IH V IL f V(y)=V(x) Switching Threshold Nominal Voltage Levels V OH = f(V IL ) V OL = f(V IH ) V M = f(V(X) per V(x) = V(y)

40 40 Mapping between analog and digital signals V IL V IH V in Slope = -1 V OL V OH V out 0 V OL V IL V IH V OH Undefined Region 1

41 41 Definition of Noise Margins Noise margin high Noise margin low V IH V IL Undefined Region "1" "0" V OH V OL NM H L Gate Output Gate Input

42 42 Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources

43 43 Key Reliability Properties Absolute noise margin values are deceptive –a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric – the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;

44 44 Regenerative Property Regenerative Non-Regenerative

45 45 Regenerative Property A chain of inverters v 0 v 1 v 2 v 3 v 4 v 5 v 6 Simulated response

46 46 Fan-in and Fan-out N Fan-out N Fan-in M M

47 47 The Ideal Gate R i = R o = 0 Fanout = NM H = NM L = V DD /2 g = V in V out

48 48 An Old-time Inverter NM H V in (V) NM L V M

49 49 Delay Definitions

50 50 Ring Oscillator T = 2 t p N

51 51 A First-Order RC Network v out v in C R t p = ln (2) = 0.69 RC Important model – matches delay of inverter

52 52 Power Dissipation Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power:

53 53 Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p

54 54 A First-Order RC Network v out v in CLCL R

55 55 Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this book Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation

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